Matches 351 - 400 out of 632 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >
Match Document Document Title
6602773 Methods of fabricating semiconductor devices having protected plug contacts and upper interconnections  
Embodiments of methods of fabricating protected contact plugs include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming an...
6599644 Method of making an ohmic contact to p-type silicon carbide, comprising titanium carbide and nickel silicide  
A method of producing an ohmic contact to p-type silicon carbide comprising two layers, the first one comprising nickel silicide and the second one comprising titanium carbide is disclosed. The...
6596616 Method for forming serrated contact opening in the semiconductor device  
A method and apparatus for decreasing contact resistance between a ohmic contact ( 120 ) and a semiconductor material ( 106 ) are disclosed. Increased contact resistance, which occurs as a result...
6593176 METHOD FOR FORMING PHASE-CHANGE MEMORY BIPOLAR ARRAY UTILIZING A SINGLE SHALLOW TRENCH ISOLATION FOR CREATING AN INDIVIDUAL ACTIVE AREA REGION FOR TWO MEMORY ARRAY ELEMENTS AND ONE BIPOLAR BASE CONTACT  
The invention relates to a process of forming a phase-change memory device. The process includes forming a salicide structure in peripheral logic portion of the substrate and preventing forming...
6589890 Precleaning process for metal plug that minimizes damage to low-&kgr dielectric  
The invention is a precleaning process suitable for fabricating metal plugs in a low-κ, carbon-containing dielectric. More specifically, the invention is a process for cleaning a contact area of a...
6579785 Method of making multi-level wiring in a semiconductor device  
A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating...
6576939 Semiconductor processing methods, methods of forming electronic components, and transistors  
In one implementation, first and second layers are formed over a substrate. One of the layers has a higher oxidation rate than the other when exposed to an oxidizing atmosphere. The layers...
6573171 Semiconductor device and manufacturing process thereof  
In a peripheral circuit region requiring a conductive path between layers at the periphery of a memory cell array region, a conductive path is provided, after removing a silicon nitride film used...
6569752 Semiconductor element and fabricating method thereof  
The present semiconductor element comprises a semiconductor substrate, a wiring pad formed thereon, a layer of barrier metal formed thereon, an intermetallic compound Ag 3 Sn formed thereon, and a...
6566239 Semiconductor device manufacturing method having a step of forming a post terminal on a wiring by electroless plating  
A method of manufacturing a semiconductor device is provided. The method includes the steps of forming a wiring layer on an underlying metal film formed on a substrate, the wiring layer being...
6559033 Processing for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines  
Protective caps are formed over horizontally closely spaced apart metal lines of an integrated circuit structure. Low k silicon oxide dielectric material is then deposited over and between the...
6559030 Method of forming a recessed polysilicon filled trench  
A method of forming a recessed polysilicon contact is provided. The method includes: forming a trench in a substrate; overfilling the trench with polysilicon; removing the polysilicon outside of...
6555450 Contact forming method for semiconductor device  
A contact forming method of a semiconductor device is disclosed, in which a pad polysilicon layer is formed at an active region of a cell array, thereafter an upper portion of a gate is opened when...
6555457 Method of forming a laser circuit having low penetration ohmic contact providing impurity gettering and the resultant laser circuit  
A novel contact structure and method for a multilayer gettering contact metallization is provided utilizing a thin layer of a pure metal as the initial layer formed on a semiconductor cap layer....
6551877 Method of manufacturing memory device  
A method of manufacturing a memory device. A substrate having an active region, a plurality of gate structures and a plurality of source/drain regions are provided. An inter-layer dielectric layer...
6551914 Method of forming polish stop by plasma treatment for interconnection  
A semiconductor device in which an interconnection material is buried in a hole formed in an interlevel insulating film arranged on a semiconductor substrate includes a protective layer formed on...
6551923 Dual width contact for charge gain reduction  
A method of forming a contact in an integrated circuit is disclosed herein. The method includes providing a first insulating layer over a semiconductor substrate including first and second gate...
6551915 Thermal annealing/hydrogen containing plasma method for forming structurally stable low contact resistance damascene conductor structure  
Within a damascene method for forming a patterned conductor layer within an aperture defined by a patterned dielectric layer within a microelectronic fabrication, at least one of: (1) the patterned...
6548390 SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY (DRAM) CIRCUITRY  
Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a...
6548389 Semiconductor device and method for fabricating the same  
After an insulating film serving as a gate insulating film is formed on a semiconductor substrate, a titanium nitride film is deposited by chemical vapor deposition on the insulating film. Then, a...
6548347 Method of forming minimally spaced word lines  
A method of forming minimally spaced word lines is disclosed. A double exposure technique is employed at the gate formation level. A small trench is defined through gate stack layers by using a...
6544674 Stable electrical contact for silicon carbide devices  
An electrical contact for a silicon carbide component comprises a material that is in thermodynamic equilibrium with silicon carbide. The electrical contact is typically formed of Ti 3 SiC 2 that...
6534397 Pre-treatment of low-k dielectric for prevention of photoresist poisoning  
Deleterious poisoning of patterned photoresist masking layers accompanying plasma ashing/etching of photoresist and/or low-k dielectric layers is eliminated, or at least substantially reduced, by...
6531382 Use of a capping layer to reduce particle evolution during sputter pre-clean procedures  
A process for preparing a surface of a lower level metal structure, exposed at the bottom of a sub-micron diameter opening, to allow a low resistance interface to be obtained when overlaid with an...
6524952 Method of forming a titanium silicide layer on a substrate  
A method of forming a silicide layer in contact with a silicon substrate. The method comprises forming the silicide layer by supplying a silicon-containing source that is different from the silicon...
6521527 Semiconductor device and method of fabricating the same  
Obtained are a semiconductor device which can prevent diffusion of an impurity contained in a gate electrode and a method of fabricating the same. In this semiconductor device, a gate oxide film...
6518153 Method for making gate electrodes of low sheet resistance for embedded dynamic random access memory devices  
A method of making embedded DRAM devices having integrated therein a gate electrode of low sheet resistance satisfying the requirement of high performance logic circuitry is provided. The gate...
6518157 Methods of planarizing insulating layers on regions having different etching rates  
An insulating layer can be formed on first and second adjacent regions of an integrated circuit having a first step difference therebetween, the first and second regions having first and second...
6514844 Sidewall treatment for low dielectric constant (low K) materials by ion implantation  
A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises densifying a...
6511912 Method of forming a non-conformal layer over and exposing a trench  
In a copper plating process, a seed layer is uniformly deposited over a surface, including lining a high aspect ratio trench defined by that surface. A mask layer is provided using a process that...
6500315 Method and apparatus for forming a layer on a substrate  
A method and an apparatus for forming a layer on a substrate are disclosed. In accordance with one embodiment, a substrate ( 901 ) is placed into a chamber ( 30 ) that includes a coil ( 16 ) and a...
6495454 Substrate interconnect for power distribution on integrated circuits  
A backside interconnect structure is used to deliver power through the substrate to the front side of an integrated circuit. One or more power planes are formed on the backside of the substrate and...
6495439 Method for suppressing pattern distortion associated with BPSG reflow and integrated circuit chip formed thereby  
Significant amounts of pattern distortion were found to be the result of reflowing borophosphosilicate glass (BPSG) and silicon dioxide shrinkage during high temperature junction anneals. In order...
6495294 Method for manufacturing semiconductor substrate having an epitaxial film in the trench  
A trench is formed in a silicon substrate, and an epitaxial film is formed on the substrate and in the trench. After a part of the epitaxial film formed around an opening portion of the trench is...
6485654 Method of fabricating self-aligned contacts  
A process for producing a self-aligned contact comprises the steps of forming leads on a substrate, forming an etching stop layer on the leads by depositing, then forming a sacrificed oxide layer;...
6486049 Method of fabricating semiconductor devices with contact studs formed without major polishing defects  
In a semiconductor device, a contact stud ( 100 ) contacts a semiconductor substrate ( 10 ); the stud is embedded in an insulating structure with a first insulating layer ( 20 ) and a second...
6479355 Method for forming landing pad  
The present invention provides a method for landing pads in the semiconductor devices, comprising the following steps: providing a semiconductor substrates with a plurality of active regions, a...
6475895 Semiconductor device having a passivation layer and method for its fabrication  
A semiconductor device structure and process for its fabrication includes a first layer of HDP oxide and an overlying layer of silicon oxynitride. Application of the HDP oxide to a pattern of metal...
6476497 Concentric metal density power routing  
A method for concentric metal density power distribution is disclosed that reduces metal density and increases available area for routing clock and signal traces. A method of concentric metal...
6475812 Method for fabricating cladding layer in top conductor  
A method for cladding two or three sides of a top conductor for a magnetic memory device in ferromagnetic material includes forming a trench with side walls in a coating layer above the memory...
6475891 Method of forming a pattern for a semiconductor device  
A method of forming a pattern for a semiconductor device without using a photolithography technique is disclosed, wherein the method includes forming a sacrificial layer on a semiconductor...
6476488 Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections  
A method for making a novel structure having borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections on integrated circuits is achieved. An etch-stop...
6472303 Method of forming a contact plug for a semiconductor device  
A method of manufacturing a semiconductor device having the steps of forming an insulating layer on a silicon substrate, forming a contact hole on the insulating layer, forming a selective silicon...
6472302 Integration method for raised contact formation for sub-150 nm devices  
An integrated raised contact formation method to achieve ultra shallow junction devices is described. Semiconductor device structures are provided in and on a substrate and covered with a...
6468889 Backside contact for integrated circuit and method of forming same  
A contact formed from the backside of an integrated circuit device includes a first conductive layer on a first surface of the integrated circuit device and a second conductive layer on a second...
6468904 RPO process for selective CoSix formation  
A method for forming an improved RPO layer by using a composite layer and a two-step etching process in a salicide process in the fabrication of integrated circuits is described. Isolation areas...
6468890 Semiconductor device with ohmic contact-connection and method for the ohmic contact-connection of a semiconductor device  
The disclosed semiconductor device comprises an ohmic contact between a semiconductor region made of n-conducting silicon carbide and a largely homogeneous ohmic contact layer ( 110 ), which...
6458680 Method of fabricating contact pads of a semiconductor device  
An upper insulating layer is formed on a semiconductor substrate, the upper insulating layer having an etch selection ratio relative to a lower insulating layer. The upper insulating layer is...
6455407 Methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random access memory (DRAM) circuitry  
Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a...
6451694 Control of abnormal growth in dichloro silane (DCS) based CVD polycide WSix films  
In a process for mitigating and/or eliminating the abnormal growth of underlying polysilicon in dichloro silane-based CVD polycide WSix films, a first technique conducts the deposition of the...
Matches 351 - 400 out of 632 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >