Matches 501 - 550 out of 631 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >
Match Document Document Title
6197670 Method for forming self-aligned contact  
A method for forming a self-aligned contact includes forming a second insulating layer, on a first insulating layer including a first self-aligned contact pad formed on a semiconductor substrate,...
6194302 Integrated process flow to improve the electrical isolation within self aligned contact structure  
A method of fabrication of a top half spacer on a first spacer on a gate structure for a self aligned contact (SAC) process. The method begins by providing at least two spaced gate structures...
6194301 Method of fabricating an integrated circuit of logic and memory using damascene gate structure  
An integrated circuit device is presented. The integrated circuit device of the present invention comprises a semiconductor substrate having a combination of transistor gates formed using a...
6191020 Conductive interconnection for semiconductor integrated circuit and method of forming the same  
A conductive interconnection for an integrate circuit between a protected node and a protecting node and its method are disclosed. The conductive interconnection comprises a stacking connector, a...
6190911 Semiconductor device and fabrication method thereof  
A method for fabricating a semiconductor device having a wiring part connected via an opening portion formed in an insulting film on a semiconductor region to the semiconductor region. The wiring...
6184118 Method for preventing the peeling of the tungsten metal after the metal-etching process  
The present invention is a method for preventing the peeling phenomena of the Tungsten metal in the integrated circuit after the metal-etching process. A semiconductor's substrate is provided. An...
6184119 Methods for reducing semiconductor contact resistance  
A method is provided for reducing contact resistances in semiconductors. In the use of fluorocarbon plasmas during high selectively sub-quarter-micron contact hole etching, with the silicon...
6174776 Method for forming gate contact in complementary metal oxide semiconductor  
A method for forming a gate contact is disclosed. The method includes that a semiconductor substrate and a silicon dioxide layer are provided upon the semiconductor substrate. Then, a polysilicon...
6174793 Method for enhancing adhesion between copper and silicon nitride  
A method for enhancing adhesion ability between copper and silicon nitride is disclosed. The present method comprises following steps: first, provide a substrate and then form a copper layer on the...
6171942 Methods of forming electrically conductive lines in integrated circuit memories using self-aligned silicide blocking layers  
Conductive lines are formed in integrated circuit memories using a Silicide blocking layer that is self-aligned. The Silicide blocking layer is self-aligned by etching an electrically insulating...
6169020 Methods of fabricating integrated circuits including metal silicide contacts extending between a gate electrode and a source/drain region  
The presence and absence of sidewall spacers are used to provide discontinuous and continuous contacts respectively, between a gate electrode and a source/drain region. In particular, first and...
6169019 Semiconductor apparatus and manufacturing method therefor  
In a method of manufacturing a semiconductor device, a titanium silicide layer is formed on a region of a diffusion layer formed in a semiconductor substrate. A silicon nitride film functioning as...
6159843 Method of fabricating landing pad  
A method of fabricating a landing pad. A gate electrode is formed on a substrate. The gate electrode has a top surface covered by a cap layer and a sidewall covered by a spacer. A polysilicon layer...
6159872 F ion implantation into oxide films to form low-K intermetal dielectric  
Ion implantation of fluorine into SiO 2 films results in formation of a dielectric material having a dielectric constant K≤3.2. High energies associated with ion implantation permit stable...
6150252 Multi-stage semiconductor cavity filling process  
Cavities such as vias and contacts formed in semiconductor devices are filled in a multi-stage process to provide low resistance electrical connections. A liner is first deposited into the cavity...
6150241 Method for producing a transistor with self-aligned contacts and field insulation  
A process for making a MOS transistor. The transistor includes a source, a channel and drain formed on a portion of silicon film in a silicon-on-insulator type structure. A field insulation layer...
6146991 Barrier metal composite layer featuring a thin plasma vapor deposited titanium nitride capping layer  
A process for fabricating a tungsten plug, in a deep, small diameter opening, featuring a novel adhesive-barrier composite layer, located along the sides of the deep, small diameter opening, has...
6143637 Process for production of semiconductor device and cleaning device used therein  
The present invention provides a process for producing a semiconductor device, which comprises: a step of forming a metal wiring pattern on a semiconductor wafer, a step of arranging a plurality of...
6140218 Method for fabricating a T-shaped hard mask/conductor profile to improve self-aligned contact isolation  
The present invention provides a method of fabricating a T-shaped hard mask/conductive pattern profile and a process of etching a self-aligned contact opening using a T-shaped hard mask/conductive...
6136677 Method of fabricating semiconductor chips with silicide and implanted junctions  
A method of fabricating a semiconductor device includes the steps of providing a semiconductor chip (10) with a memory area (22) and a logic area (26). The memory area (22) and the logic area (26)...
6136680 Methods to improve copper-fluorinated silica glass interconnects  
A method of forming an interconnect, comprising the following steps. A semiconductor structure is provided that has an exposed first metal contact and a dielectric layer formed thereover. An FSG...
6133133 Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component  
An electrical contact and method for making an electrical contact to a node location is disclosed and which includes forming a substrate having a node location to which electrical connection is to...
6130150 Method of making a semiconductor device with barrier and conductor protection  
A method of making a semiconductor device includes forming at least one opening, having vertical sidewalls and a bottom, in a first dielectric layer adjacent a substrate. A second dielectric layer...
6124192 Method for fabricating ultra-small interconnections using simplified patterns and sidewall contact plugs  
A process for fabricating an interconnect structure, featuring contact of the interconnect structure, to an exposed side of an underlying conductive plug structure, where the conductive plug...
6124197 Adjusting the size of conductive lines based upon contact size  
The present invention is directed to a method of forming conductive interconnections in an integrated circuit device to optimize or at least maintain the speed at which signals propagate throughout...
6121102 Method of electrical connection through an isolation trench to form trench-isolated bipolar devices  
In order to produce an electrical connection to an inner layer such as a bottom diffusion (103), which has a good electrical conductivity and is located inside a bipolar semiconductor device...
6121135 Modified buried contact process for IC device fabrication  
A new method of forming a butted contact and a buried contact having low contact resistance in the fabrication of integrated circuits is described. A first layer of polysilicon is deposited over a...
6121127 Methods and devices related to electrodes for p-type group III nitride compound semiconductors  
An electrode for a Group III nitride compound semiconductor having p-type conduction that has a double layer structure. The first metal electrode layer comprising, for example, nickel (Ni) and the...
6117757 Method of forming landing pads for bit line and node contact  
A method of forming landing pads for a bit line and a node contact is provided. First, a first dielectric layer is formed on a substrate having a transistor structure thereon. The first dielectric...
6117758 Etch removal of aluminum islands during manufacture of semiconductor device wiring layer  
In a method of manufacturing a semiconductor device, a first wiring layer is formed on a semiconductor substrate. An interlevel insulating film is formed on the semiconductor substrate to cover the...
6117762 Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering  
A method and apparatus for protecting semiconductor integrated circuits from reverse engineering. Semiconductor active areas are formed on a substrate. A silicide layer is formed both over at least...
6117755 Method for planarizing the interface of polysilicon and silicide in a polycide structure  
A method for planarizing the interface of polysilicon and silicide in a polycide structure is presented in this invention. It is by regulating the process temperature when depositing polysilicon to...
6117760 Method of making a high density interconnect formation  
A technique is provided for forming interconnects laterally spaced from each other across a semiconductor topography by a deposited dielectric spacer layer. The lateral distance between each...
6117765 Method of preventing cracks in insulating spaces between metal wiring patterns  
A semiconductor device having a metal layer pattern which prevents cracks from forming in insulating spaces. The semiconductor device includes a plurality of metal layers stacked vertically and a...
6110817 Method for improvement of electromigration of copper by carbon doping  
A method for forming a carbon doped copper layer, preferably an electrochemically deposited carbon doped copper layer over a semiconductor structure, comprising the following steps. A semiconductor...
6110813 Method for forming an ohmic electrode  
A first metal film and a second metal film, both of which are made of Ni or the like, are deposited on the upper surface of a substrate made of SiC. In such a state, the interface between the first...
6110823 Method of modifying the thickness of a plating on a member by creating a temperature gradient on the member, applications for employing such a method, and structures resulting from such a method  
Contact structures exhibiting resilience or compliance for a variety of electronic components are formed by bonding a free end of a wire to a substrate, configuring thw wire into a wire stem having...
6110814 Film forming method and semiconductor device manufacturing method  
The present invention relates to a film forming method for forming a planarized interlayer insulating film to cover wiring layers, etc. of a semiconductor integrated circuit device. The method...
6107177 Silylation method for reducing critical dimension loss and resist loss  
A method for reducing critical dimension loss and resist loss dimensions during etching includes providing a dielectric layer having an anti-reflection layer formed thereon and patterning a resist...
6107175 Method of fabricating self-aligned contact  
A method of a method of fabricating a contact. A substrate having a plurality of gates and a plurality of lightly doped source/drain regions is provided. A dielectric layer is formed and patterned...
6103593 Method and system for providing a contact on a semiconductor device  
A method for providing at least one contact on a semiconductor is disclosed. The semiconductor includes a plurality of isolation structures. The method and system include providing an etch-stop...
6100181 Low dielectric constant coating of conductive material in a damascene process for semiconductors  
A method for manufacturing an integrated circuit using damascene processes is provided in which planar surfaces subjected to chemical-mechanical polishing are protected by a protective low...
6093627 Self-aligned contact process using silicon spacers  
A method of forming self-aligned contact by using silicon spacers is provided. The process comprising: forming gate structures on a semiconductor substrate, the gate structure comprising a layer of...
6093602 Method to form polycide local interconnects between narrowly-spaced features while eliminating stringers  
A method of fabricating local interconnects of polycide has been achieved. A substrate is provided. Narrowly spaced features, such as MOS transistor gates and polysilicon traces, are provided...
6093628 Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application  
A method for fabricating a deep sub-micron gate electrode, comprising polysilicon and metal, having ultra-low sheet resistance. The process begins by forming shallow trench isolation regions 14 in...
6093629 Method of simplified contact etching and ion implantation for CMOS technology  
A method for forming n- and p-type contacts for CMOS integrated circuits is described wherein the contact openings are ion implanted after being etched to provide supplemental doping to the exposed...
6093634 Method of forming a dielectric layer on a semiconductor wafer  
The present invention provides a method of forming a dielectric layer on a semiconductor wafer. The semiconductor wafer comprises a bottom dielectric layer and a plurality of metal lines each...
6090695 Method for forming self-aligned landing pads  
A method for forming self-aligned landing pads on a substrate containing a pre-formed first conducting layer and a pre-formed first insulator, wherein the substrate further includes a patterned...
6090694 Local interconnect patterning and contact formation  
A method for forming a semiconductor device to produce a more distortion free via for interconnecting levels within a device or forming a connection between an external surface and an internal...
6083782 High performance GaAs field effect transistor structure  
An improved GaAs MESFET includes a source contact ohmically coupled to a buffer layer or substrate to stabilize band bending at the interface of the active layer and buffer layer or substrate when...
Matches 501 - 550 out of 631 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >