|
Match
|
Document |
Document Title |
|
|
6319806 |
Integrated circuit wiring and fabricating method thereof
The present invention relates to an integrated circuit wiring capable of reducing the contact resistance between lines and a fabricating method thereof. The wiring in accordance with the present...
|
|
|
6316311 |
Method of forming borderless contact
A method of forming borderless contacts is provided. A substrate is provided. The substrate has at least a logic region and a memory region. A MOS transistor and a STI structure are formed on the...
|
|
|
6316353 |
Method of forming conductive connections
A method of forming a conductive connection between a first region and a second region includes forming a first titanium comprising layer over and in electrical connection with the first region....
|
|
|
6316345 |
High-temperature fluorinated chemistry removal of contact BARC layer
An anti-reflective coating layer which is used to provide better control over the photolithographic process during the contact masking step is removed using high-temperature fluorine containing...
|
|
|
6313023 |
Method of fabricating deflection aperture array for electron beam exposure apparatus, wet etching method and apparatus for fabricating the aperture array, and electron beam exposure apparatus having the aperture array
A method of fabricating a deflection aperture array used in an electron beam exposure apparatus and a wet etching method and apparatus for fabricating the deflection aperture array are disclosed....
|
|
|
6306750 |
Bonding pad structure to prevent inter-metal dielectric cracking and to improve bondability
A process of forming a bond pad structure, with a roughened top surface topography, used to improve the bondability of a gold wire bond, to the underlying bond pad structure, has been developed....
|
|
|
6300245 |
Inductively coupled plasma powder vaporization for fabricating integrated circuits
An apparatus and method for performing material deposition on semiconductor devices. The apparatus provides an enclosure for defining a chamber. The chamber includes a metallic portion such as a...
|
|
|
6297138 |
Method of depositing a metal film onto MOS sensors
A method for depositing a metal film onto the semiconductor substrate and insulator of a MOS sensor is provided. The method utilizes a laser ablation technique to deposit metal films having a...
|
|
|
6297139 |
Method of forming a contact hole in a semiconductor wafer
The present invention provides a method of forming a contact hole of a DRAM on a semiconductor wafer. The semiconductor wafer comprises a substrate, a conductive layer positioned in a predetermined...
|
|
|
6294449 |
Self-aligned contact for closely spaced transistors
A pair of transistors sharing a common electrodes e.g. a bitline in a DRAM array, has a self-aligned contact to the bitline in which the transistor gate stack has only a poly layer with a nitride...
|
|
|
6294451 |
Semiconductor device and method for manufacturing the same
Semiconductor device and method for manufacturing the same prevent the spread of a tungsten film out of an opening portion of a contact hole when the tungsten is grown in the contact hole and avoid...
|
|
|
6294457 |
Optimized IMD scheme for using organic low-k material as IMD layer
A method of metallization wherein particle issues are avoided during pre-metal cleaning by the use of a unique IMD scheme is described. A semiconductor substrate is provided which may include...
|
|
|
6291334 |
Etch stop layer for dual damascene process
The present invention provides a carbon based etch stop, such as a diamond like amorphous carbon, having a low dielectric constant and a method of forming a dual damascene structure. The low k etch...
|
|
|
6281143 |
Method of forming borderless contact
A method for forming borderless contact is disclosed. The method includes providing a substrate with active areas and a trench isolation region in which the active areas are silcide. Then, the...
|
|
|
6274471 |
Method for making high-aspect-ratio contacts on integrated circuits using a borderless pre-opened hard-mask technique
A method for fabricating high-aspect-ratio contacts on integrated circuits, such as embedded DRAMs, using a borderless pre-opened hard-mask technique is achieved. After forming gate electrodes for...
|
|
|
6274468 |
Method of manufacturing borderless contact
A method of manufacturing borderless contact can compensate for misalignment that occurs during formation of the contacts. First, a substrate with a gate structure on it is provided. The substrate...
|
|
|
6271107 |
Semiconductor with polymeric layer
Bumped semiconductor substrates and methods for forming bumped semiconductor substrates are disclosed. The bumped semiconductor substrates have a polymeric layer, which can serve as a passivation...
|
|
|
6271111 |
High density pluggable connector array and process thereof
The present invention relates generally to high density pluggable connector array and process thereof. More particularly, the invention encompasses a structure comprising high density pluggable...
|
|
|
6271131 |
Methods for forming rhodium-containing layers such as platinum-rhodium barrier layers
A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula L y RhY z is provided. Also provided is a chemical vapor co-deposited...
|
|
|
6271114 |
System for adjusting the size of conductive lines based upon the contact size
The present invention is directed to a method of forming conductive interconnections in an integrated circuit device to optimize or at least maintain the speed at which signals propagate throughout...
|
|
|
6271108 |
Method of forming a contact in semiconductor device
The present invention relates to a method of forming a contact in semiconductor device, more particularly, to a method of forming a borderless contact in semiconductor device which minimizes loss...
|
|
|
6268274 |
Low temperature process for forming inter-metal gap-filling insulating layers in silicon wafer integrated circuitry
This invention provides an in situ low temperature, two step deposition HDP-CVD process separated by a cooldown period, for forming an inter-metal dielectric passivation layer for an integrated...
|
|
|
6265298 |
Method for forming inter-metal dielectrics
An improved method for forming inter-metal dielectrics (IMD) over a semiconductor substrate is provided, wherein a conductive line is formed thereon. A first dielectric layer is formed over the...
|
|
|
6265296 |
Method for forming self-aligned contacts using a hard mask
A method for making self-aligned contacts on a semiconductor substrate using a hard mask. After the transistor is formed, a blanket insulating layer is formed on said semiconductor substrate. A...
|
|
|
6261965 |
Effective removal of undesirably formed silicon carbide during the manufacture of semiconductor device
A manufacturing method of a semiconductor device removes a silicon carbide layer, which is undesirably formed on a surface or the like of a contact hole by dry etching, by plasma treatment using a...
|
|
|
6258720 |
Method of formation of conductive lines on integrated circuits
The present invention relates to a method of formation of a conductive line on integrated circuits including the steps of etching a first insulator layer to create therein openings of predetermined...
|
|
|
6258727 |
Method of forming metal lands at the M0 level with a non selective chemistry
The starting structure consists of a silicon substrate having diffused regions formed therein and gate conductor stacks formed thereupon that is passivated by a TEOS layer as standard. At a further...
|
|
|
6255207 |
Composite planarizing dielectric layer employing high density plasma chemical vapor deposited (HDP-CVD) underlayer
A method for forming upon a substrate employed within a microelectronics fabrication a composite dielectric layer having etched via contact holes in which via poisoning is attenuated. There is...
|
|
|
6248654 |
Method for forming self-aligned contact
A method of forming a self-aligned contact in a semiconductor device comprising a semiconductor substrate and a gate line. The method comprises the steps of forming a conductive layer on an overall...
|
|
|
6248655 |
Method of fabricating a surface shape recognition sensor
A surface shape recognition sensor of this invention includes at least a plurality of capacitance detection elements having sensor electrodes arranged in the same plane on an interlevel dielectric...
|
|
|
6245654 |
Method for preventing tungsten contact/via plug loss after a backside pressure fault
A method for preventing tungsten contact/via plug loss after a backside pressure fault defect in a deposition chamber is provided. In the method, first deposited by a silane soak step and a...
|
|
|
6245658 |
Method of forming low dielectric semiconductor device with rigid, metal silicide lined interconnection system
Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigration performance by removing the inter-layer dielectrics and...
|
|
|
6245653 |
Method of filling an opening in an insulating layer
The present invention is about a method for filling an opening in an insulating layer in a fast and highly reliable way and can be used to fill openings such as trenches and via holes...
|
|
|
6239015 |
Semiconductor device having polysilicon interconnections and method of making same
A doped polysilicon layer is used to form interconnections in a semiconductor device through contact holes. The doped polysilicon layer reaches through contact holes formed in an interlayer...
|
|
|
6239356 |
Process for stampable photoelectric generator
Manufacture of a photoelectric converter by a photolithographic or stamping process prior to coating with a photoelectrically emissive material is described. This gives an economic and simple means...
|
|
|
6232220 |
Method for fabricating a semiconductor component having a low contact resistance with respect to heavily doped zones
A method for fabricating a semiconductor component having a low contact resistance with respect to heavily doped or siliconized zones in a semiconductor body. Fluorine ions are implanted into the...
|
|
|
6228731 |
Re-etched spacer process for a self-aligned structure
A process for forming a self-aligned contact, (SAC), structure, on an active device region in a semiconductor substrate, exposed at the bottom of a SAC opening in an insulator layer, has been...
|
|
|
6225204 |
Method for preventing poisoned vias and trenches
A method for preventing the occurrence of poisoned trenches and vias in a dual damascene process that includes performing a densification process, such as an implantation process, on the surface of...
|
|
|
6221747 |
Method of fabricating a conductive plug with a low junction resistance in an integrated circuit
An integrated circuit (IC) fabrication method is provided for fabricating a conductive plug, such as a contact plug or a via plug, with a low junction resistance in an integrated circuit. This...
|
|
|
6218277 |
Method for filling a via opening or contact opening in an integrated circuit
An integrated circuit includes a substrate (12) having a conductive region (18), and includes a dielectric layer (19) disposed over the substrate. An upwardly tapering frustoconical opening (22) is...
|
|
|
6218278 |
Method of forming a conducting structure
The method of forming a conducting structure consists in applying to a substrate a 2 to 20 nm thick layer of a material transformable into conducting one under the effect of radiation, and...
|
|
|
6214715 |
Method for fabricating a self aligned contact which eliminates the key hole problem using a two step spacer deposition
This invention provides a method for forming a self aligned contact without key holes using a two step sidewall spacer deposition. The process begins by providing a semiconductor structure having a...
|
|
|
6214742 |
Post-via tin removal for via resistance improvement
A method of manufacturing a semiconductor device having metal structures formed on a first layer of interlayer dielectric, wherein the metal structures have a layer of TiN formed on the surface of...
|
|
|
6211051 |
Reduction of plasma damage at contact etch in MOS integrated circuits
A method of fabricating contacts to device elements of an integrated circuit on a semiconductor substrate that includes: (a) using a plasma process to form a first hole in the material above a...
|
|
|
6211050 |
Fill pattern in kerf areas to prevent localized non-uniformities of insulating layers at die corners on semiconductor substrates
A method for making a planar spin-on-glass (SOG) layer over integrated circuits at the corners of the chip (die) areas is achieved. This method allows more reliable integrated circuits to be made,...
|
|
|
6207545 |
Method for forming a T-shaped plug having increased contact area
A method for forming a T-shaped contact plug is disclosed. A first insulating layer is formed atop of a substrate. A second insulating layer is then formed atop of the first insulating layer. The...
|
|
|
6207483 |
Method for smoothing polysilicon gate structures in CMOS devices
There is provided a method for smoothing the surface of undoped polysilicon regions of a CMOS structure, primarily gate regions. A direct HPD-CVD argon sputter is used improve the surface roughness...
|
|
|
6200888 |
Method of producing semiconductor device comprising insulation layer having improved resistance and semiconductor device produced thereby
A semiconductor device comprising an insulation film covering a semiconductor chip so as to expose electrodes or pads fabricated in the chip and wiring lines located on the insulation film and...
|
|
|
6197675 |
Manufacturing method for semiconductor device having contact holes of different structure
A semiconductor memory device comprises a semiconductor substrate, a first conducting layer formed above the main surface of the semiconductor substrate, a second conducting layer formed above the...
|
|
|
6197674 |
CVD-Ti film forming method
A method of forming a CVD-Ti film includes the steps of loading a Si wafer into a chamber, setting an interior of the chamber at a predetermined reduced-pressure atmosphere, introducing TiCl 4 ...
|