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6995080 Methods of forming transistor gates  
The invention includes a method of forming a transistor gate. One or more conductive materials are formed over a semiconductor substrate, and a block is formed over the one or more conductive...
6984562 Method for forming dielectric layer between gates in flash memory device  
The present invention provides a method for preventing an oxide film from becoming thick due to the reaction of the oxide film and a floating gate in a method for manufacturing a flash memory...
6984530 Method of fabricating a MRAM device  
A method of fabricating a magnetic random access memory (MRAM) device is disclosed. The method reduces the number of mask steps and processing steps required to fabricate the MRAM device. A first...
6972226 Charge-trapping memory cell array and method for production  
In a memory cell array comprising charge-trapping memory cells, local interconnects along the direction of the wordlines for connecting source/drain regions of adjacent memory cells to bitlines are...
6972229 Method of manufacturing self-aligned non-volatile memory device  
A method of forming a self-aligned non-volatile device, includes, in part: forming trench isolation regions, forming a well between the trench isolation, forming a second well above the first well,...
6963104 Non-volatile memory device  
A non-volatile memory device includes a substrate, an insulating layer, a fin, a number of dielectric layers and a control gate. The insulating layer is formed on the substrate and the fin is...
6963106 Memory array with memory cells having reduced short channel effects  
According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing a dielectric material from an isolation region situated in a substrate to...
6962841 Suppression of cross diffusion and gate depletion  
According to the present invention, an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the...
6960495 Method for making contacts in a high-density memory  
A method for forming a contact in a three dimensional monolithic memory is disclosed. In a preferred embodiment, the method comprises depositing a conductive layer over and in contact with a...
6958270 Methods of fabricating crossbar array microelectronic electrochemical cells  
The present invention provides microelectronic electrochemical structures and related fabrication methods. A composite microelectronic structure is provided that includes first and second...
6958269 Memory device with reduced cell size  
A method for manufacturing a memory device includes forming an oxide layer adjacent a substrate. A floating gate layer is formed and disposed outwardly from the oxide layer. A dielectric layer is...
6958272 Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell  
A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is...
6946346 Method for manufacturing a single electron memory device having quantum dots between gate electrode and single electron storage element  
In a method for manufacturing a single electron memory device including a single electron storage element in a gate lamination pattern formed on a nano-scale channel region of a MOSFET, formation...
6939764 Methods of forming memory cells having self-aligned silicide  
Concurrently forming self-aligned silicides on word lines and contacts of a memory device facilitates reduced resistance and/or reduced device sizing. The word-line silicide is formed at a stage...
6933219 Tightly spaced gate formation through damascene process  
The invention includes an apparatus and a method of manufacturing such apparatus using a damascene process. The method includes the step of patterning a layer disposed over a substrate to include a...
6933194 Method of manufacturing semiconductor device using STI technique  
A method of manufacturing a semiconductor device including forming a laminate structure which includes a gate insulation film on a semiconductor substrate and a gate electrode material film on the...
6924522 EEPROM transistor for a DRAM  
A floating gate transistor is formed by simultaneously creating buried contact openings on both EEPROM transistor gates and DRAM access transistor source/drain diffusions. Conventional DRAM process...
6924155 Ferroelectric memory, method of fabricating the same, semiconductor device, and method of fabricating the same  
A method of manufacturing a ferroelectric memory of the present invention includes applying pulsed laser light 70 to a ferroelectric capacitor 105 from above the ferroelectric capacitor in a...
6924220 Self-aligned gate formation using polysilicon polish with peripheral protective layer  
A method of protecting a peripheral region, by forming a protective mask over the peripheral area, during polysilicon polishing while forming self-aligned polysilicon gates in flash memory...
6916707 High coupling floating gate transistor  
The present invention provides methods of fabricating floating gate transistors. One method includes forming laterally spaced source and drain regions to define a channel therebetween, forming a...
6903408 Flash memory cell with high programming efficiency by coupling from floating gate to sidewall  
A new method to form flash memory devices in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A first film is formed comprising a first oxide...
6897111 Method using quasi-planar double gated fin field effect transistor process for the fabrication of a thyristor-based static read/write random-access memory  
A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a horizontal semiconductor fin on top of the semiconductor substrate. An access...
6887756 Method of forming flash memory with protruded floating gate  
A method of forming a flash memory with a protruded floating gate. A substrate is provided. An isolation area and a plurality of patterned conductive layers are sequentially formed on the...
6881628 Vertical flash memory cell with buried source rail  
A non-volatile memory cell has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a control gate are fabricated vertically...
6881629 Method to make minimal spacing between floating gates in split gate flash  
A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises...
6878988 Non-volatile memory with induced bit lines  
An electrically programmable non-volatile memory cell is provided. A semiconductor substrate is prepared. A pair of spaced apart source/drain (S/D) regions is defined on the semiconductor...
6855563 Method of manufacturing a tunnel magneto-resistance based magnetic memory device  
In a method of manufacturing a magnetic memory device comprising a writing word line (first wiring) and a bit line (second wiring) three-dimensionally orthogonally intersecting therewith, with a...
6849501 Methods for fabricating an improved floating gate memory cell  
Methods for fabricating improved floating gate memory cells are provided. A substrate and a first insulating layer are fabricated, where the first insulating layer is formed on the substrate. A...
6847068 Floating gate and fabrication method therefor  
A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has...
6841444 Nonvolatile semiconductor memory device and manufacturing method thereof  
A nonvolatile semiconductor memory device that can be miniaturized is provided. A method of manufacturing the nonvolatile semiconductor memory device includes the steps of: forming an interlayer...
6818505 Non-volatile semiconductor memory device and manufacturing method thereof  
In a non-volatile semiconductor memory device, three-layered structure of the first, second and third floating gate electrodes is implemented, and stepped portions are provided on the first...
6815347 Method of forming a reflective electrode  
The present invention provides a method of forming a TFT and a reflective electrode having recesses or projections with reduced manufacturing cost and a reduced number of manufacturing steps, and...
6812096 Method for fabrication a flash memory device having self-aligned contact  
A flash memory device that comprises a self-aligned contact opening and a fabrication method thereof are described. Subsequent to the formation of the control gate of the flash memory device, a...
6809402 Reflowable-doped HDP film  
Device leakage due to spacer undercutting is remedied by depositing a B-doped HDP or a BP-doped HDP oxide gap filling layer capable of flowing into undercut regions. Embodiments include depositing...
6808995 Semiconductor device with minimal short-channel effects and low bit-line resistance  
A transistor device that includes at least two transistors, each transistor including a source region, a drain region, and a shallow trench isolation formed between and contiguous with the source...
6809019 Method for producing a semiconductor structure, and use of the method  
A method for producing a semiconductor structure includes applying at least one first layer, etching the first layer using a masking layer such that fences are produced, and, after removal of the...
6806517 Flash memory having local SONOS structure using notched gate and manufacturing method thereof  
A notched gate SONOS transistor includes: a substrate having source/drain regions; a gate insulator layer on the substrate between the source/drain regions; a notched gate structure, on the gate...
6803299 Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping  
An electrically erasable programmable read only memory (EEPROM) having a non conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as...
6800526 Method for manufacturing a self-aligned split-gate flash memory cell  
A method for manufacturing a split-gate flash memory cell, comprising the steps of forming an active region on a semiconductor substrate; forming a buffer layer on the semiconductor substrate;...
6797563 Method of forming cross point type DRAM cell  
A dynamic random access memory (DRAM) device comprises a substrate, a plurality of substantially parallel word lines, and a plurality of substantially parallel bit lines. A plurality of memory...
6797566 Semiconductor integrated circuit device and process for producing the same  
A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions 205 formed in first conduction type well 201 , floating gates ...
6784057 Semiconductor device and nonvolatile semiconductor memory device comprising a plurality of semiconductor elements as well as process for the same  
A semiconductor device of which the process is simplified so that the manufacturing cost can be reduced and, at the same time, which has a semiconductor element that can control a current of high...
6784041 Semiconductor device and method of manufacturing the same  
A NAND type semiconductor device is disclosed, in which a first insulating film embedded between the memory cell gates and between the memory cell gates and the selecting gate does not contain...
6780712 Method for fabricating a flash memory device having finger-like floating gates structure  
A finger-like floating gate structure in flash memory cells is disclosed. Raised isolation regions within a semiconductor region separate parallel active regions. A gate dielectric layer is...
6777291 Methods of forming programmable memory devices comprising tungsten  
The invention includes a method of making a programmable memory device. At least one floating gate layer is formed over a semiconductor substrate. A dielectric material is formed over the at least...
6777741 Non-volatile memory cells with selectively formed floating gate  
Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or...
6773990 Method for reducing short channel effects in memory cells and related structure  
According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing a dielectric material from an isolation region situated in a substrate to...
6773988 Memory wordline spacer  
A manufacturing method for a memory and a memory made thereby includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted...
6773974 Method of forming a semiconductor array of floating gate memory cells and strap regions  
A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, along with strap regions interlaced within the array. The array includes...
6770520 Floating gate and method of fabricating the same  
A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which a gate dielectric layer, a conducting layer, and a patterned hard mask layer are sequentially formed....
Matches 151 - 200 out of 482 < 1 2 3 4 5 6 7 8 9 10 >