Match Document Document Title
6518130 Method for forming a semiconductor device having a DRAM region and a logic region on the substrate  
A semiconductor device comprising a plurality of first transistors formed in a first region of a semiconductor substrate and a plurality of second transistors formed in a second region of the...
6518125 Method for forming flash memory with high coupling ratio  
First of all, a semiconductor substrate has the poly regions thereon. Then the souse/drain regions are formed in the semiconductor substrate by performing the ion-implant method. Next, the...
6518154 Method of forming semiconductor devices with differently composed metal-based gate electrodes  
MOS transistors and CMOS devices comprising a plurality of transistors including metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket...
6514827 Method for fabricating a dual metal gate for a semiconductor device  
A method for fabricating a dual metal gate structure for a semiconductor device including deposition of a semiconductor substrate having PMOS and NMOS regions, a first gate having a first...
6514841 Method for manufacturing gate structure for use in semiconductor device  
A method for manufacturing a gate structure for use in a semiconductor device including the steps of sequentially forming a gate oxide layer, a polysilicon layer, a tungsten layer and a nitride...
6514859 Method of salicide formation with a double gate silicide  
A method of forming a self-aligned silicide (salicide) with a double gate silicide. The method improves transistor speed by lowering the leakage current in the source and drain areas and lowering...
6511882 Method for preventing the leakage path in embedded non-volatile memory  
A method for forming an embedded non-volatile memory is disclosed. The embedded non-volatile memory, comprises memory array and logic device area, is formed on a substrate where an...
6509254 Method of forming electrode structure and method of fabricating semiconductor device  
After depositing a first metal film of a first metal on a silicon-containing film including silicon as a main component, a second metal film of a nitride of a second metal is deposited on the first...
6509253 T-shaped gate electrode for reduced resistance  
An integrated circuit includes a transistor with a T-shaped gate conductor. The T-shaped gate conductor can achieve a lower sheet resistance characteristic. The transistor can include a silicided...
6506670 Self aligned gate  
A method for making a gate in an integrated circuit. A gate layer is formed on a substrate, and a blocking layer is formed on the gate layer. The blocking layer is masked with a photoresist layer,...
6506649 Method for forming notch gate having self-aligned raised source/drain structure  
An innovative MOSFET having a raised source drain (RSD) is constructed prior to implanting source-drain dopants. The RSD structure thus built has a distinct advantage in that the offset from the...
6506642 Removable spacer technique  
Submicron-dimensioned MOS and/or CMOS transistors are fabricated utilizing a simplified removable sidewall spacer technique, enabling effective tailoring of individual transistors to optimize their...
6504210 Fully encapsulated damascene gates for Gigabit DRAMs  
A fully polysilicon encapsulated metal-containing damascene gate structure is provided that is useful in Gigabit DRAM (dynamic random access memory) device. The fully encapsulated metal-containing...
6503806 Method for forming gate electrode of a semiconductor device with dual spacer to protect metal portion of gate  
Disclosed is a method for forming a gate electrode of a semiconductor device, the method comprises the steps of: stacking a gate oxide film, a doped first silicon film, a diffusion preventing film,...
6500743 Method of copper-polysilicon T-gate formation  
A method for manufacturing a field effect transistor ( 100 ) includes forming a gate structure ( 104 ) on a surface of a semiconductor substrate and forming first and second spacers ( 126, 126 ) on...
6498082 Method of forming a polysilicon layer  
A method of forming a polysilicon layer includes the steps of: loading a semiconductor substrate in a CVD reactor wherein a gate insulating layer is formed on the substrate; decompressing the...
6498080 Transistor fabrication method  
A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define...
6498067 Integrated approach for controlling top dielectric loss during spacer etching  
A process for forming a composite insulator spacer on the sides of a MOSFET gate structure, has been developed. The process features formation of additional insulator spacer shapes on top portions...
6495437 Low temperature process to locally form high-k gate dielectrics  
A method of forming a dielectric gate insulator in a transistor is disclosed herein. The method includes providing a gate structure including a layer of material over a semiconductor structure,...
6495438 Titanium polycide gate electrode and method of forming a titanium polycide gate electrode of a semiconductor device  
The present invention provides a method of forming a titanium polycide gate electrode. The method comprises the step of: forming a gate insulation film a top surface of a semiconductor substrate;...
6492250 Polycide gate structure and method of manufacture  
A polycide gate structure and a method of forming the polycide gate. A substrate having a gate dielectric layer, a polysilicon layer, a silicide layer and an insulation layer thereon is provided....
6489236 Method for manufacturing a semiconductor device having a silicide layer  
A method for forming a MOSFET includes the steps of forming cobalt silicide layers on a polysilicon gate electrode and source/drain regions, implanting impurity ions to form source/drain extensions...
6489210 Method for forming dual gate in DRAM embedded with a logic circuit  
A method for forming a dual gate of a semiconductor device includes the steps of sequentially stacking a gate insulating film, a semiconductor layer, and a low resistance metal layer on a...
6482726 Control trimming of hard mask for sub-100 nanometer transistor gate  
A method is provided, the method including forming a gate dielectric layer above a substrate layer, forming a gate conductor layer above the gate dielectric layer, forming a first hard mask layer...
6482738 Method of locally forming metal silicide layers  
The present invention mainly provides a method to locally form metal silicide on an integral circuit and to avoid the phenomenon of leakage current which is caused by metal silicide formed between...
6479373 Method of structuring layers with a polysilicon layer and an overlying metal or metal silicide layer using a three step etching process with fluorine, chlorine, bromine containing gases  
Doped polysilicon layers and layered polysilicon structures are produced, and the layers and layered structures are structured. The doping is distinguished by the fact that the doping compound is...
6479379 Self-aligned etch stop for polycrystalline silicon plugs on a semiconductor device  
A method for providing a self-aligned etch stop layer comprises the steps of providing a dielectric layer having a polycrystalline silicon (poly) plug formed therein. An aluminum layer is formed to...
6468857 Method for forming a semiconductor device having a plurality of circuits parts  
Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of salicide structure are provided together, and a method of manufacturing the same. Each gate...
6468888 Method for forming polysilicon-germanium gate in CMOS transistor and device made thereby  
A method for making a ULSI MOSFET chip includes forming transistor gates on a substrate and a semiconductor device thereby made. The gates are formed by depositing a polysilicon layer on the...
6465295 Method of fabricating a semiconductor device  
A semiconductor device fabrication method comprises the steps of forming a gate insulating film on a surface of a semiconductor substrate, forming a polysilicon film on the gate insulating film,...
6465309 Silicide gate transistors  
A semiconductor structure and method for making the same provides a gate dielectric formed of oxynitride or a nitride/oxide stack formed within a recess. Amorphous silicon is deposited on the gate...
6465334 Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors  
High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in...
6465284 Semiconductor device and method for manufacturing the same  
A method for manufacturing a semiconductor device comprises the steps of forming a semiconductor film on a substrate, oxidizing a surface of said semiconductor film in an oxidizing atmosphere with...
6461951 Method of forming a sidewall spacer to prevent gouging of device junctions during interlayer dielectric etching including silicide growth over gate spacers  
A method and arrangement for forming a recessed spacer to prevent the gouging of device junctions during a contact etch or local interconnect etch process deliberately overetches the spacer...
6458641 Method for fabricating MOS transistors  
In PMOS having a gate electrode 7 of a p-type polysilicon film 5 along with a silicon nitride film 13, boron diffusion from the p-type polysilicon film 5 and boron punching through the gate...
6458702 Methods for making semiconductor chip having both self aligned silicide regions and non-self aligned silicide regions  
A semiconductor process is provided that creates fully-salicided transistors. in a first region and partially-salicided transistors in a second region. Each of the fully-salicided transistors...
6458678 Transistor formed using a dual metal process for gate and source/drain region  
A method for forming a semiconductor device includes providing a substrate and forming a gate stack on the substrate. The gate stack includes a gate electrode having a thickness. Source/drain...
6458679 Method of making silicide stop layer in a damascene semiconductor structure  
A damascene gate semiconductor structure that is formed utilizing a silicide stop layer. Initially, a gate opening is provided in an insulating layer on a substrate. A first dielectric layer is...
6455389 Method for preventing a by-product ion moving from a spacer  
This invention relates to a method that prevents by-productions from moving from a spacer. In particular by using an offset liner, a liner with a treated surface and a spacer that is formed by...
6455406 Semiconductor processing method of forming a conductive connection through WxSiyNz material with specific contact opening etching  
A conductive structure includes a conductively doped semiconductive material and an overlying W x Si y N z comprising material, where each of “x”, “y” and “z” is greater than zero....
6455383 Methods of fabricating scaled MOSFETs  
The scaled MOSFETs having a conductive barrier-metal layer sandwiched between a metal layer or a thick silicide layer on the top and a first conductive gate layer at the bottom are disclosed by the...
6451694 Control of abnormal growth in dichloro silane (DCS) based CVD polycide WSix films  
In a process for mitigating and/or eliminating the abnormal growth of underlying polysilicon in dichloro silane-based CVD polycide WSix films, a first technique conducts the deposition of the...
6451679 Ion mixing between two-step titanium deposition process for titanium salicide CMOS technology  
A new method of forming selective salicide is described, whereby low resistance salicide is formed on exposed MOSFET CMOS, narrow polysilicon gates and lightly doped source/drains (LLD) without...
6451658 Graded layer for use in semiconductor circuits and method for making same  
Methods of forming a graded layer is disclosed. The graded layer transitions from one material to another material. The properties of these materials are chosen to optimize the interfaces on each...
6448120 Totally self-aligned transistor with tungsten gate  
A totally self-aligned transistor with a tungsten gate. A single mask is used to align the source, drain, gate and isolation areas. Overlay error is greatly reduced by the use of a single mask for...
6448140 Laterally recessed tungsten silicide gate structure used with a self-aligned contact structure including a straight walled sidewall spacer while filling recess  
A process for fabricating composite insulator spacers, comprised of an underlying silicon oxide sidewall layer, and an overlying silicon nitride layer, formed on the sides of a polycide gate...
6444579 Methods of forming low resistivity titanium silicide structures  
Methods and apparatus for forming a conductor layer utilize an implanted matrix to form C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.25 micron...
6440829 N-profile engineering at the poly/gate oxide and gate oxide/SI interfaces through NH3 annealing of a layered poly/amorphous-silicon structure  
A method and structure providing N-profile engineering at the poly/gate oxide and gate oxide/Si interfaces of a layered polysilicon/amorphous silicon structure of a semiconductor device. NH 3 ...
6440808 Damascene-gate process for the fabrication of MOSFET devices with minimum poly-gate depletion, silicided source and drain junctions, and low sheet resistance gate-poly  
A sub-0.1 μm MOSFET device having minimum poly depletion, salicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene-gate process wherein the...
6440826 NiSi contacting extensions of active regions  
Smaller active regions are enabled by forming nickel suicide extensions from the nickel silicide layers on the source/drain regions and landing contacts on the nickel silicide extensions. The...