Matches 301 - 350 out of 1060 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
6743645 Method of inspecting process for manufacturing semiconductor device and method of manufacturing semiconductor device  
A method of inspecting a process for manufacturing a semiconductor device, used to determine the status of a processing operation during the manufacturing process, according to the embodiment of...
6740570 Method for forming a self-aligned silicide of a metal oxide semiconductor  
The present invention discloses a method for forming a self-aligned silicidation of a metal oxide semiconductor. The feature of the present invention is to perform an ionic implanting step before...
6740550 Methods of manufacturing semiconductor devices having chamfered silicide layers therein  
A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate;...
6737343 Method for manufacturing an integrated circuit structure with limited source salicidation  
A method for forming metal salicide regions and metal salicide exclusion regions in an integrated circuit (IC) that requires a minimum number of steps and is compatible with standard MOS processing...
6737310 Self-aligned process for a stacked gate RF MOSFET device  
A process for fabricating an RF type, MOSFET device, concentrating on reducing performance degrading gate resistance, has been developed. The process features formation of a stacked gate structure,...
6734427 TEM/SEM sample preparation  
A method of preparing a test sample for electron microscopy analysis is disclosed. First, a chip segment is attached to a holder of a sample polisher, and a first polishing end of the chip segment...
6734099 System for preventing excess silicon consumption in ultra shallow junctions  
The present invention provides a system for preventing excess silicon consumption in a semiconductor wafer by depositing a metal layer ( 114 ) on top of a native oxide layer above a silicide layer...
6734089 Techniques for improving wordline fabrication of a memory device  
Fabrication techniques for making a semiconductor device. More specifically, techniques for fabricating a wordline in a memory device are provided. Specific heat treatments may be added to the...
6730588 Method of forming SiGe gate electrode  
The present invention provides a method of forming SiGe gate electrodes using a thin nucleation layer. A dielectric layer is formed on a semiconductor wafer and a thin silicon nucleation layer...
6730587 Titanium barrier for nickel silicidation of a gate electrode  
Nickel silicidation of a gate electrode is controlled using a titanium barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a...
6727166 Removal of silicon oxynitride material using a wet chemical process after gate etch processing  
A method is presented for forming a transistor gate structure. A gate oxide layer is formed. Gate material is deposited on the gate oxide layer. A layer of silicon oxynitride is deposited on the...
6723608 Method for manufacturing a semiconductor device having a layered gate electrode  
A method for manufacturing a DRAM includes the steps of forming a gate oxide film, a polysilicon film and a tungsten silicide film consecutively on a silicon substrate, selective etching the...
6723609 Method of preventing leakage current of a metal-oxide semiconductor transistor  
A gate oxide layer and a gate are sequentially formed on a substrate, and a source/drain extension is formed in the substrate thereafter. A liner layer is then formed to cover the substrate, and a...
6723625 Semiconductor device having thin electrode laye adjacent gate insulator and method of manufacture  
Disclosed is a semiconductor device (e.g., nonvolatile semiconductor memory device) and method of forming the device. The device includes a gate electrode (e.g., floating gate electrode) having a...
6720225 Reactive pre-clean using reducing gas during nickel silicide process  
A method of manufacturing a MOSFET semiconductor device comprises providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; providing a...
6720226 Semiconductor device and method for facticating the same  
Gate insulating film, gate electrode made up of lower and upper gate electrodes, and on-gate passivation film are formed in this order on an Si substrate. Then, a sidewall is formed as a stack of...
6716735 Method for forming metal lines of semiconductor device  
After first metal lines and a first inter-metal dielectric are formed on a semiconductor substrate, top surfaces thereof are planarized to construct a flat plane. Then, second metal lines each...
6716734 Low temperature sidewall oxidation of W/WN/poly-gatestack  
In a method of making a W/WN/Poly-Gatestack, the improvement of providing low temperature sidewall oxidation to affect less outdiffusion of dopant implants near the surface to allow more margin in...
6713372 Method for manufacturing synchronous DRAM device  
The present invention provides a method of synchronous dynamic random access memory (SDRAM), including the steps of: preparing a semiconductor substrate on which a gate insulating layer, a stacked...
6703297 Method of removing inorganic gate antireflective coating after spacer formation  
Various methods of manufacturing are disclosed. In one aspect, a method of manufacturing is provided that includes forming an anti-reflective coating on a structure on a substrate. A first spacer...
6696725 Dual-gate MOSFET with channel potential engineering  
A semiconductor device with reduced hot carrier injection and punch through is formed with a dual gate electrode comprising edge conductive portions, a central conductive portion, and dielectric...
6696333 Method of making integrated circuit with MOSFETs having bi-layer metal gate electrodes  
A method of fabricating integrated circuits includes forming MOSFETs with gate electrodes of a first composition, and sidewall spacers along laterally opposed sides of those gate electrodes,...
6696354 Method of forming salicide  
A method of forming a salicide. A metal layer is formed on a silicon-based substrate comprising a gate with a spacer on the side wall of the gate and a source/drain is provided. Next, a first...
6693022 CVD method of producing in situ-doped polysilicon layers and polysilicon layered structures  
Doped polysilicon layers and layered polysilicon structures are produced, and the layers and layered structures are structured. The doping is distinguished by the fact that the doping compound is...
6693032 Method of forming a contact structure having an anchoring portion  
A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are provided....
6690070 Insulated gate semiconductor device and its manufacturing method  
A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer 8 superimposed on the polysilicon layer, and a part of the second...
6680474 Semiconductor calibration wafer with no charge effect  
A semiconductor calibration wafer that has no charge effect is disclosed. The calibration wafer has a substrate layer and a conductive metal layer. The conductive metal layer completely covers the...
6677189 Method for forming polysilicon thin film transistor with a self-aligned LDD structure  
A polysilicon thin film transistor with a self-aligned LDD structure has a polysilicon layer formed on a transparent insulating substrate. The polysilicon layer consists of a channel region, an LDD...
6677224 Method of forming stacked gate for flash memories  
The method of the present invention includes the steps of forming doped regions in the semiconductor substrate. A pad oxide layer is formed on the semiconductor substrate. A masking layer is formed...
6673665 Semiconductor device having increased metal silicide portions and method of forming the semiconductor  
The surface area of silicon lines which receives a silicide portion is increased to decrease the line resistance in narrow polysilicon lines, such as gate electrodes. Sidewall spacers are formed...
6673706 Method of forming a pattern using a photoresist without exposing the photoresist and silicidation method incorporating the same  
A photoresist pattern is formed, without being exposed, by using photoresist having a residual layer proportion characteristic by which the photoresist dissolves at a suitable rate in a developing...
6667227 Trenched gate metal oxide semiconductor device and method  
A Metal Oxide Semiconductor (MOS) transistor and method for improving device scaling comprises a trenched polysilicon gate formed within a trench etched in a semiconductor substrate and further...
6667228 Method for fabricating cell plugs of semiconductor device  
A method for fabricating cell plugs of a semiconductor device is disclosed, which increases the operation speed of the semiconductor device by reducing the cell plug resistance of the device. The...
6657244 Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation  
A method of fabricating a semiconductor structure where a low gate resistance is obtained, while simultaneously reducing silicon consumption in the source/drain diffusion regions. The method...
6653225 Method for forming gate electrode structure with improved profile and gate electrode structure therefor  
A gate electrode, in which the slope of the profile of a gate electrode forming material layer, for example, a refractory metal silicide layer is prevented from being decreased due to thermal...
6649500 Semiconductor device including an insulated gate field effect transistor and method of manufacturing the same  
A semiconductor device is disclosed including an IGFET (insulated gate field effect transistor) and a method of manufacturing the same. The semiconductor device may include an oxide film ( 115 ) or...
6645818 Method to fabricate dual-metal gate for N- and P-FETs  
A new method for forming a dual-metal gate CMOS transistors is described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A nitride layer is...
6645840 Multi-layered polysilicon process  
A method for forming a notched MOS gate structure is described. A multi-layer gate structure is formed ( 150 ) where the top layer ( 140 ) oxidizes at a faster rate compared to the bottom layer (...
6642592 Semiconductor device and method for fabricating same  
A semiconductor device and method for fabricating the same which improves reliability of the semiconductor device is disclosed. The semiconductor device includes: a first insulating film and a gate...
6638843 Method for forming a silicide gate stack for use in a self-aligned contact etch  
A method for forming a gate stack having a silicide layer that can subsequently undergo a SAC etch is disclosed. The present method provides a layer of insulating material on top of the silicide...
6635539 Method for fabricating a MOS transistor using a self-aligned silicide technique  
A method for fabricating a MOS transistor using a self-aligned silicide technique is provided. The method includes forming a gate electrode and a silicidation resistant layer pattern that are...
6632715 Semiconductor device having nonvolatile memory cell and field effect transistor  
A semiconductor device in which a nonvolatile memory cell with a floating gate electrode and a field effect transistor are formed on a semiconductor substrate includes a first conductive layer, a...
6630399 Titanium disilicide resistance in pinched active regions of semiconductor devices  
A method of manufacturing a semiconductor device ( 2 ) on a substrate ( 1 ), the semiconductor device including an active area ( 5, 6, 16 ) in the substrate ( 1 ) demarcated by spacers (...
6630394 System for reducing silicon-consumption through selective deposition  
Disclosed is a system for fabricating a semiconductor device ( 100 ). A layer of cobalt ( 32 ) is deposited onto a silicon region ( 104, 106, 108 ) and annealed to form a cobalt silicide layer (...
6627527 Method to reduce metal silicide void formation  
A method of forming a low resistance metal silicide layer on a narrow width, conductive gate structure, has been developed. After formation of a metal silicide layer on a conductive gate structure...
6627526 Method for fabricating a conductive structure for a semiconductor device  
A process for making semiconductor structures, and the resulting highly conductive semiconductor structures, includes using damascene process to form a structure with a thin adhesive layer and...
6627525 Method for preventing polycide gate spiking  
A method for preventing polycide gate spiking, which essentially comprises the following steps: forms an oxide layer on a substrate; forming a polysilicon layer on the oxide layer; sputtering a...
6624489 Formation of silicided shallow junctions using implant through metal technology and laser annealing process  
A method for producing MOS type transistors with deep source/drain junctions and thin, silicided contacts with desireable interfacial and electrical properties. The devices are produced by a method...
6624057 Method for making an access transistor  
Methods are disclosed for the fabrication of novel polysilicon structures having increased surface areas to achieve lower resistances after silicidation. The structures are applicable, for example,...
6620718 Method of forming metal silicide regions on a gate electrode and on the source/drain regions of a semiconductor device  
The present invention is directed to a method of forming metal silicide regions on a gate electrode ( 23 ) and on the source/drain regions ( 25 ) of a semiconductor device ( 100 ). In one...
Matches 301 - 350 out of 1060 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >