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6436775 MOSFET device fabrication method capable of allowing application of self-aligned contact process while maintaining metal gate to have uniform thickness  
The MOSFET fabrication method allows application of a self-aligned contact (SAC) process while maintaining a metal gate, such as a tungsten gate, to have a uniform thickness. The process involves...
6432805 Co-deposition of nitrogen and metal for metal silicide formation  
Salicide processing is implemented with silicon nitride sidewall spacers by initially depositing a refractory metal, e.g., Ni, in the presence of nitrogen to form a metal nitride layer to prevent...
6432801 Gate electrode in a semiconductor device and method for forming thereof  
The present invention relates to a method for forming a gate electrode in a semiconductor device, which can improve GOI characteristics and allows for an effective suppression of metal silicide...
6432817 Tungsten silicide barrier for nickel silicidation of a gate electrode  
Nickel silicidation of a gate electrode is controlled using a tungsten silicide barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon...
6432804 Sputtered silicon target for fabrication of polysilicon thin film transistors  
A method of forming a thin film device includes preparing a substrate; forming a silicon target having predetermined impurities therein; depositing a layer of amorphous silicon by physical vapor...
6429110 MOSFET with both elevated source-drain and metal gate and fabricating method  
A method of forming a transistor and a semiconductor-metal-oxide transistor. The method at least includes provides a substrate; covers the substrate by a doped amorphous polysilicon layer and a...
6429101 Method of forming thermally stable polycrystal to single crystal electrical contact structure  
A method for forming a thermally stable ohmic contact structure that includes a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. At least one region of...
6423633 Method for manufacturing diffusion barrier layer  
A method for manufacturing a diffusion barrier layer over a substrate having a patterned copper layer. A refractory metal layer is formed on the substrate and a top surface and a sidewall of the...
6423634 Method of forming low resistance metal silicide region on a gate electrode of a transistor  
In one embodiment, a protective layer is formed on the top surface of the gate electrode of a transistor device prior to the formation of low resistance metal silicide regions on the drain and...
6423632 Semiconductor device and a process for forming the same  
A semiconductor device and a process for forming the device includes a conductor that overlies an insulating layer. In one embodiment, the conductor includes a first conductive portion, a second...
6420264 Method of forming a silicide region in a Si substrate and a device having same  
A method of forming a silicide region ( 80 ) on a Si substrate ( 10 ) in the manufacturing of semiconductor integrated devices, a method of forming a semiconductor device (MISFET), and a device...
6417104 Method for making a low resistivity electrode having a near noble metal  
A method for forming conductive lines such as interconnects and DRAM gate stacks. A blanket stack is formed on a substrate including a conductive diffusion barrier, a near noble metal such as...
6417099 Method for controlling dopant diffusion in a plug-shaped doped polysilicon layer on a semiconductor wafer  
The present invention provides a method for controlling dopant density of a plug-shaped doped polysilicon layer formed within a plug-shaped recess to prevent the dopant contained in the plug-shaped...
6413841 MOS type semiconductor device and manufacturing method thereof  
First, a polysilicon film is formed on a gate oxide film. Next, a polysilicon oxide film is formed on the polysilicon film. Thereafter, the polysilicon film is thermally treated to allow a crystal...
6410411 Electronic device and their manufacture  
A thin-film circuit element such as a top-gate TFT has good quality electrical contacts formed between an electrode ( 151, 152, 155 ) of chromium nitride and the semiconductor film ( 50 ) of the...
6410392 Method of producing MOS transistor  
The surface of a silicon substrate is sputter-etched so that silicon clusters sputtered out form a silicon film on a side wall spacer. Then, a metal film of cobalt, titanium or the like is built up...
6410428 Nitride deposition on tungsten-polycide gate to prevent abnormal tungsten silicide oxidation  
A method of forming a non-oxidized WSi x layer on a semiconductor wafer, including the following steps. A semiconductor wafer having a silicon substrate is provided within a CVD tool. A WSi x ...
6407436 Semiconductor device with abrupt source/drain extensions with controllable gate electrode overlap  
A method for forming source/drain extensions with gate overlap. An oxide layer is formed on a semiconductor substrate and a gate structure on the semiconductor substrate. First, sidewall spacer...
6406952 Process for device fabrication  
A process for device fabrication, comprising the steps of forming a dielectric material region on a silicon substrate, forming a first amorphous silicon or polysilicon region on the dielectric...
6406743 Nickel-silicide formation by electroless Ni deposition on polysilicon  
The present invention provides a method of manufacturing a nickel-silicide technology for polysilicon interconnects. Nickel 40 is deposited on polysilicon 30 using a electroless process. Using...
6406985 Method of fabricating buried contact  
A method of fabricating a buried contact. On a substrate having a shallow trench isolation thereon, a gate oxide layer and a polysilicon layer are sequentially formed. The polysilicon layer and the...
6403458 Method for fabricating local interconnect structure for integrated circuit devices, source structures  
A process for making a local interconnect and the structures formed thereby. The process is practiced by forming a Ti layer having a nitrogen-rich upper portion over a portion of a substrate,...
6399468 Semiconductor device and method of manufacturing the same  
To increase the withstand voltage and reduce ON-state resistance, a semiconductor device provided with a gate electrode formed on a semiconductor substrate via a gate insulating film, an LP layer...
6399493 Method of silicide formation by silicon pretreatment  
Various methods of fabricating a silicide film and structures incorporating the same are provided. In one aspect, a method of fabricating a silicide film is provided that includes providing a...
6399452 Method of fabricating transistors with low thermal budget  
A low thermal budget transistor is fabricated by first forming a gate on a semiconductor substrate. First amorphous regions and first inactive dopant regions are then created in the substrate by...
6399467 Method of salicide formation  
A method of forming a self-aligned silicide (salicide) with a screening oxide. The method improves transistor speed by lowering the leakage current in the source and drain areas and lowering the...
6399485 Semiconductor device with silicide layers and method of forming the same  
The present invention provides a semiconductor device having: at least a first diffusion layer having a first impurity concentration; at least a second diffusion layer having a first impurity...
6395595 Multi-layer tunneling device with a graded stoichiometry insulating layer  
An improved and novel multi-layer thin film device including a graded-stoichiometry insulating layer ( 16 ) and a method of fabricating a multi-layer thin film device including a...
6391704 Method for manufacturing an MDL semiconductor device including a DRAM device having self-aligned contact hole and a logic device having dual gate structure  
A method for manufacturing an MDL semiconductor device comprises forming a gate insulating layer and a gate conductive layer in a DRAM device region and a logic device region to provide gate...
6391754 Method of making an integrated circuit interconnect  
A method of encapsulating metal lines ( 130, 132, 134, 136, 138 ) by implantation of dopants to form surface regions ( 131, 133, 135, 137, 139 ) after the metal lines have been fabricated. The...
6387803 Method for forming a silicide region on a silicon body  
The invented method produces a silicide region on a silicon body that is useful for a variety of purposes, including the reduction of the electrical contact resistance to the silicon body or an...
6387790 Conversion of amorphous layer produced during IMP Ti deposition  
A method of fabricating a Ti-containing liner having good contact resistance and coverage of a contact hole is provided. The method which converts an amorphous region of ionized metal plasma...
6387767 Nitrogen-rich silicon nitride sidewall spacer deposition  
Salicide processing is implemented with nitrogen-rich silicon nitride sidewall spacers that allow a metal silicide layer e.g., NiSi, to be formed over the polysilicon gate electrode and...
6387788 Method for forming polycide gate electrode of metal oxide semiconductor field effect transistor  
The present invention provides a method for fabricating an improved gate electrode of a MOSFET device. And the method for fabricating a MOSFET device having a polycide gate to which a titanium...
6383906 Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption  
A method for forming ultra shallow junctions in a semiconductor wafer uses disposable spacers and a silicon cap layer to achieve ultra-low low silicon consumption during a salicide formation...
6383878 Method of integrating a salicide process and a self-aligned contact process  
A method of integrating salicide process and self-aligned contact process is performed on a semiconductor substrate on which a plurality of doped gate electrodes and source/drain regions are formed...
6383905 Formation of micro rough poly surface for low sheet resistance salicided sub-quarter micron poly lines  
This invention relates to a method for manufacturing a semiconductor device having polysilicon lines with micro-roughness on the surface. The micro-rough surface of the polysilicon lines help...
6380057 Enhancement of nickel silicide formation by use of nickel pre-amorphizing implant  
Nickel salicide processing is implemented by implanting nickel into the active regions, prior to depositing Ni, to catalyze the reaction of Ni and Si during annealing to form a NiSi layer on the...
6380055 Dopant diffusion-retarding barrier region formed within polysilicon gate layer  
A diffusion-retarding barrier region is incorporated into the gate electrode to reduce the downward diffusion of dopant toward the gate dielectric. The barrier region is a nitrogen-containing...
6376348 Reliable polycide gate stack with reduced sheet resistance and thickness  
Formation of a gate having a polysilicon and silicide layer thereover with reduced resistance and reduced thickness is provided. The polysilicon layer is annealed to diffuse the dopants out from...
6376351 High Fmax RF MOSFET with embedded stack gate  
A method for forming a wide gate stack over a gate in a rf device is described. The invention reduces the gate resistance and the Rs significantly. A substrate has a digital area and a rf area....
6376349 Process for forming a semiconductor device and a conductive structure  
Semiconductor devices and conductive structures can be formed having a metallic layer. In one embodiment, a semiconductor device includes an amorphous metallic layer ( 22 ) and a crystalline...
6376298 Layout method for scalable design of the aggressive RAM cells using a poly-cap mask  
A method for integrating salicide and self-aligned contact processes in the fabrication of integrated circuits by using a poly cap mask and a special layout technique is described. A pair of gate...
6376372 Approaches for mitigating the narrow poly-line effect in silicide formation  
A silicide process using a pre-anneal amorphization implant prior to silicide anneal. A layer of titanium is deposited and reacted to form titanium silicide ( 32 ) and titanium nitride. The...
6376350 Method of forming low resistance gate electrode  
The present invention is directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of polysilicon and forming a recess in the...
6376319 Process to fabricate a source-drain extension  
A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been...
6376320 Method for forming field effect transistor with silicides of different thickness and of different materials for the source/drain and the gate  
For fabricating a field effect transistor having a gate structure on a gate dielectric within an active device area of a semiconductor substrate, a hardmask dielectric material covers a top surface...
6373112 Polysilicon-germanium MOSFET gate electrodes  
An insulated gate field effect transistor (FET) of a particular conductivity type, has as a gate electrode including a polycrystalline SiGe layer. A process in accordance with the present invention...
6372616 Method of manufacturing an electrical interconnection of a semiconductor device using an erosion protecting plug in a contact hole of interlayer dielectric layer  
A method of manufacturing an electrical interconnection of a semiconductor device produces an erosion protecting plug in a contact hole to protect a selected portion of an interlayer dielectric...
6368949 Post-spacer etch surface treatment for improved silicide formation  
Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices have been reduced or a minimal junction leakage are formed by a salicide process wherein carbonaceous residue on...
Matches 451 - 500 out of 1060 < 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 >