Matches 351 - 400 out of 517 < 1 2 3 4 5 6 7 8 9 10 11 >
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6271094 Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance  
Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/μm...
6265261 Semiconductor device and fabricating method therefor in which a netride layer in a capacitor is formed in a shortened time period  
A method of fabricating a semiconductor device includes nitriding a native oxide layer on a pattern of polysilicon layers to be used as the lower electrode of a capacitor in LPCVD equipment at a...
6258675 High K gate electrode  
A semiconductor structure with a high-K insulative layer. An insulative layer is disposed on a silicon substrate and includes a first nitride layer and a high-K layer. A gate is disposed on the...
6251761 Process for polycrystalline silicon gates and high-K dielectric compatibility  
A gate stack (104) including a gate dielectric with reduced effective electrical thickness. A high-k dielectric (108) is formed over the silicon substrate (102). Remote plasma nitridation of the...
6248635 Process for fabricating a bit-line in a monos device using a dual layer hard mask  
A process for fabricating a MONOS device having a buried bit-line includes providing a semiconductor substrate and forming an ONO structure to overlie the semiconductor substrate. Thereafter, a...
6245616 Method of forming oxynitride gate dielectric  
A method for forming an oxynitride gate dielectric in a semiconductor device and gate dielectric structure formed by the method are disclosed. In the method, an oxynitride layer is first formed on...
6245605 Method to protect metal from oxidation during poly-metal gate formation in semiconductor device manufacturing  
A method for protecting metal (112) from oxidation during various oxidation steps such as CVD SiO2 oxidation for forming an overlying oxide layer (114), smile oxidation, and sidewall (116)...
6245652 Method of forming ultra thin gate dielectric for high performance semiconductor devices  
The present invention is directed to a semiconductor device having an ultra thin, reliable gate dielectric and a method for making same. In one illustrative embodiment, the present method comprises...
6242332 Method for forming self-aligned contact  
The size of a pad in the present invention is reduced, thereby preventing a polymer etch-stop, suppressing a short between a gate and a gate conductive layer exposed by the damage of an oxide layer...
6232241 Pre-oxidation cleaning method for reducing leakage current of ultra-thin gate oxide  
A new method of pre-oxidation cleaning of a substrate surface is described. The surface of a semiconductor substrate of a wafer is cleaned using a multiple step cleaning process wherein the final...
6228724 Method of making high performance MOSFET with enhanced gate oxide integration and device formed thereby  
Transistors formed according to the present invention include an oxide layer/nitride layer gate insulator and a silicide gate conductor. An oxide layer is formed to a thickness of between 15 and 25...
6225169 High density plasma nitridation as diffusion barrier and interface defect densities reduction for gate dielectric  
A method of constructing a gate dielectric on a semiconductor surface includes cleaning a silicon surface then growing a silicon nitride barrier layer on the silicon surface using a high density...
6221712 Method for fabricating gate oxide layer  
A method for fabricating a gate structure. The method involves providing a substrate, followed by forming a nitride region on a surface of the substrate. With a Tantalum (Ta)-based organic compound...
6218273 Methods of forming isolation trenches in integrated circuits using protruding insulating layers  
An isolation trench is formed from a first isolation trench in an integrated circuit substrate between active regions in the integrated circuit substrate. An insulating layer is formed in the first...
6214672 Method for manufacturing two-bit flash memory  
A method of manufacturing a two-bit flash memory. A substrate has a thin oxide layer, a silicon nitride layer and a material layer formed thereon in sequence. An opening is formed in the material...
6214712 Method of physical vapor deposition of metal oxides on semiconductors  
A process for growing a metal oxide thin film upon a semiconductor surface with a physical vapor deposition technique in a high-vacuum environment and a structure formed with the process involves...
6207591 Method and equipment for manufacturing semiconductor device  
A silicon wafer is heated from an initial pre-heating temperature (T 0 ) up to a first annealing temperature (T 1 ) by a rapid heating up step using an IR lamp. A first annealing is executed at the...
6207506 Nonvolatile memory and method for fabricating the same  
Nonvolatile memory capable of programming and erasure and method for fabricating the same, the method comprising the steps of (1) forming an oxide film on a first conduction type semiconductor...
6207541 Method employing silicon nitride spacers for making an integrated circuit device  
A process for patterning a gate of a semiconductor device is provided. A gate material layer is formed upon an oxide layer of a substrate. A photoresist layer is formed upon the gate material...
6207502 Method of using source/drain nitride for periphery field oxide and bit-line oxide  
A process for fabricating a MONOS type Flash cell device having a periphery field oxide region and a bit-line region includes providing a semiconductor substrate and growing a barrier silicon oxide...
6207543 Metallization technique for gate electrodes and local interconnects  
A process for making an integrated circuit is disclosed. This technique includes electrically interconnecting a pair of adjacent transistors positioned along a semiconductor substrate by coating...
6187633 Method of manufacturing a gate structure for a semiconductor memory device with improved breakdown voltage and leakage rate  
The invention is a method of manufacturing a semiconductor memory device using a novel intergate dielectric stack. A key feature of of the invention is the novel O/N/SiON/O structure, forming a...
6184110 Method of forming nitrogen implanted ultrathin gate oxide for dual gate CMOS devices  
A method of forming a nitrogen-implanted gate oxide in a semiconductor device includes preparing a silicon substrate; forming an oxide layer on the prepared substrate; and implanting N + or N 2 + ...
6169006 Semiconductor device having grown oxide spacers and method of manufacture thereof  
A semiconductor device having grown oxide spacers and a method for manufacturing such a semiconductor device is provided. In one embodiment of the invention, a gate electrode is formed over a...
6168968 Method of fabricating integrated thin film solar cells  
A method of fabricating an integrated thin film solar cell includes the steps of: forming a transparent conductive electrode layer and an amorphous semiconductor photoelectric conversion layer...
6162687 Method of manufacturing semiconductor device having oxide-nitride gate insulating layer  
Generally, the present invention relates to semiconductor devices having an oxide-nitride gate insulating layer and methods of manufacture thereof. Consistent with the present invention a...
6140187 Process for forming metal oxide semiconductors including an in situ furnace gate stack with varying silicon nitride deposition rate  
The present invention provides a process for forming a dopant barrier layer in a gate stack in a semiconductor device. In one advantageous embodiment, the process includes forming a gate oxide on a...
6140218 Method for fabricating a T-shaped hard mask/conductor profile to improve self-aligned contact isolation  
The present invention provides a method of fabricating a T-shaped hard mask/conductive pattern profile and a process of etching a self-aligned contact opening using a T-shaped hard mask/conductive...
6140189 Method for fabricating a LOCOS MOS device for ESD protection  
A MOS transistor having a multilevel gate oxide layer is provided for use in an ESD protection circuit. A thick gate oxide layer near the drain insures that the transistor has a relatively large...
6133106 Fabrication of a planar MOSFET with raised source/drain by chemical mechanical polishing and nitride replacement  
A method of fabricating a MOSFET includes: depositing an oxide layer on the planarized substrate; forming a silicon nitride island above a gate region in the substrate; building an oxide sidewall...
6133128 Method for patterning polysilicon gate layer based on a photodefinable hard mask process  
A process for patterning a gate of a semiconductor device is provided. A gate material layer is formed upon an oxide layer of a substrate. A photoresist layer is formed upon the gate material...
6127252 Metal-line structure in integrated circuit and method of fabricating the same  
A metal-line structure in an integrated circuit (IC) and a method of fabricating the same are provided. The metal-line structure includes a barrier layer formed at a selected location over the...
6127251 Semiconductor device with a reduced width gate dielectric and method of making same  
The present invention is directed to a semiconductor device having a reduced feature size and a method of making same. The device is comprised of a gate dielectric positioned above a semiconducting...
6124153 Method for manufacturing a polysilicon TFT with a variable thickness gate oxide  
A method for manufacturing a polysilicon thin film transistor (TFT) according to the present invention reduces the electric field near the drain junction by varying partially the thickness of a...
6114258 Method of oxidizing a substrate in the presence of nitride and oxynitride films  
A system and method of forming an oxide in the presence of a nitrogen-containing material. A substrate having a nitrogen-containing material on a surface is placed in a reaction chamber. An...
6114228 Method of making a semiconductor device with a composite gate dielectric layer and gate barrier layer  
The present invention is directed to a new semiconductor device and a method for making same. The new semiconductor device is comprised of a gate barrier layer, a composite gate dielectric layer, a...
6114182 Measurement of electron shading damage  
A resist pattern having a high-density pattern area and a low-density pattern area is formed on a layered MNOS capacitor structure composed of a Ti(O)N layer and a WSi 2 layer formed on...
6107171 Method to manufacture metal gate of integrated circuits  
The present invention discloses a method to manufacture metal gate of integrated circuits. A gate oxide layer is formed on a substrate and a polysilicon layer is then deposited on the gate oxide...
6087208 Method for increasing gate capacitance by using both high and low dielectric gate material  
A method for fabricating a MOSFET device is provided. The method includes a step of fining a gate oxide including first and second gate oxide materials. The first gate oxide material has a higher...
6087249 Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation  
An integrated circuit transistor is provided having a gate oxide and a gate conductor arranged upon a semiconductor topography, the gate oxide and gate conductor are formed within a common chamber....
6087229 Composite semiconductor gate dielectrics  
Provided are methods for fabricating hardened composite thin layer gate dielectrics. According to preferred embodiments of the present invention, composite gate dielectrics may be produced as...
6083792 Manufacturing process of a split gate flash memory unit  
A manufacturing process of a split gate flash memory unit is disclosed. The manufacturing process includes: (a) providing a silicon substrate having a first insulating layer, and forming a first...
6025228 Method of fabricating an oxynitride-capped high dielectric constant interpolysilicon dielectric structure for a low voltage non-volatile memory  
A method of fabricating an interpolysilicon dielectric structure in a non-volatile memory includes the steps of forming a high dielectric constant layer 12 on a floating gate 10 and an oxynitride...
6015739 Method of making gate dielectric for sub-half micron MOS transistors including a graded dielectric constant  
A process for fabricating a gate dielectric stack of a MOS transistor. A native oxide film is formed on an upper surface of a semiconductor substrate. A silicon nitride layer is then deposited on...
6001694 Manufacturing method for integrated circuit dielectric layer  
A method for adjusting the amount of doped nitride ions in a dielectric layer so that the nitride ions form bonds with silicon to increase the quality of an oxide layer. The method comprises the...
5960302 Method of making a dielectric for an integrated circuit  
A composite 3-layer gate dielectric is disclosed. The upper and lower layers have a concentration of nitrogen atoms, while the middle layer has very few nitrogen atoms. The presence of the nitrogen...
5943566 Method of fabricating a static random access memory  
After the formation of a gate oxide layer, a polysilicon layer is formed right away. The polysilicon layer is used for patterning the gate oxide layer. The photolithography and etching processes of...
5940682 Method of measuring electron shading damage  
A method of measuring electron shading damage which includes the steps of: a) preparing a characteristic curve of a flat band voltage change relative to an amount of injected charges, by...
5940698 Method of making a semiconductor device having high performance gate electrode structure  
A semiconductor device having a high performance gate electrode structure and a process of fabricating such a device. A semiconductor device in accordance with an embodiment of the invention is...
5927992 Method of forming a dielectric in an integrated circuit  
A method is provided for forming an improved device dielectric of a semiconductor integrated circuit, and an integrated circuit formed according to the same. For scaling geometries for use in the...
Matches 351 - 400 out of 517 < 1 2 3 4 5 6 7 8 9 10 11 >