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5972742 Method of making thin film transistor with anodic oxidation  
An improved method of forming insulated gate field effect transistors is described. In accordance with the method, gate electrodes are formed from metal such as aluminum together with wirings...
5968711 Method of dry etching A1Cu using SiN hard mask  
A new method of etching AlCu or AlSiCu lines is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an...
5970354 Poly recessed fabrication method for defining high performance MOSFETS  
A method for forming a gate conductor by using a masking layer above a polysilicon layer to define the length of a gate is presented. The length of the gate may be adjusted by the use of spacers....
5966605 Reduction of poly depletion in semiconductor integrated circuits  
A method of forming a transistor includes the steps of forming a gate structure (56) overlying a gate oxide layer (54), wherein the gate structure (56) and gate oxide layer (54) overlie a substrate...
5965911 Mos transistor adopting titanium-carbon-nitride gate electrode and manufacturing method thereof  
A MOS transistor employing a titanium-carbon-nitride (TiCN) gate electrode is provided. The MOS transistor has a gate insulating film, a gate electrode, and a source/drain region on a semiconductor...
5963841 Gate pattern formation using a bottom anti-reflective coating  
A gate is formed on a semiconductor substrate by using a bottom anti-reflective coating (BARC) to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed...
5960302 Method of making a dielectric for an integrated circuit  
A composite 3-layer gate dielectric is disclosed. The upper and lower layers have a concentration of nitrogen atoms, while the middle layer has very few nitrogen atoms. The presence of the nitrogen...
5960270 Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions  
A method for forming a metal gate MOS transistor begins by forming source and drain electrodes (26, 28, and/or 118) within a substrate (12 or 102). These source and drain regions (26, 28, and 118)...
5958508 Process for forming a semiconductor device  
A metal-semiconductor layer (26) is formed over an insulating layer (20) such that the metal-semiconductor layer (26) is graded to have varying amounts of the semiconductor and metal throughout the...
5950091 Method of making a polysilicon gate conductor of an integrated circuit formed as a sidewall spacer on a sacrificial material  
A gate conductor structure and method for forming the structure are provided whereby the overall gate length can be made with less susceptibility to lithography variations. The gate conductor is...
5946588 Low temperature sub-atmospheric ozone oxidation process for making thin gate oxides  
A process for making thin gate oxides comprising the layering of a semiconductor substrate with at least an oxide layer and a nitride layer. The layers are then patterned and etched, thereby...
5943593 Method for fabricating thin film transistor device  
A method for crystallizing a portion of a semiconductor thin film while forming a semiconductor device comprises providing a transparent substrate supporting a metallic gate electrode and an...
5943566 Method of fabricating a static random access memory  
After the formation of a gate oxide layer, a polysilicon layer is formed right away. The polysilicon layer is used for patterning the gate oxide layer. The photolithography and etching processes of...
5943574 Method of fabricating 3D multilayer semiconductor circuits  
A method of fabricating 3D semiconductor circuits including providing a conductive layer with doped polysilicon thereon patterned and annealed to form first single grain polysilicon terminals of...
5943596 Fabrication of a gate electrode stack using a patterned oxide layer  
A semiconductor device having a gate electrode stack formed using a patterned oxide layer is disclosed. The device is formed by forming an oxide layer over a surface of a substrate and forming at...
5940698 Method of making a semiconductor device having high performance gate electrode structure  
A semiconductor device having a high performance gate electrode structure and a process of fabricating such a device. A semiconductor device in accordance with an embodiment of the invention is...
5937301 Method of making a semiconductor device having sidewall spacers with improved profiles  
A semiconductor device having improved spacers and a process for fabricating the same is provided. The semiconductor device is formed by forming at least one gate electrode over a substrate and...
5937326 Method for making semiconductor device having via hole  
A method for making a semiconductor device having a via hole, includes the steps of depositing a second metal layer onto a first insulating layer formed on a semiconductor substrate where a first...
5937319 Method of making a metal oxide semiconductor (MOS) transistor polysilicon gate with a size beyond photolithography limitation by using polysilicidation and selective etching  
A method of fabricating a polysilicon gate 8 in a metal oxide semiconductor (MOS) transistor in an integrated circuit includes providing a metal layer 18, such as cobalt, on the sidewall 12 of the...
5926729 Method for forming gate oxide layers of various predefined thicknesses  
A method is provided for use in semiconductor fabrication processes for forming a plurality of gate oxide layers with various predefined thicknesses in mixed-mode or embedded circuits that are...
5923981 Cascading transistor gate and method for fabricating the same  
A cascading transistor gate structure and method for fabricating the same are disclosed. A substrate is provided, and a layer of gate dielectric material is formed over the substrate. A layer of...
5923999 Method of controlling dopant diffusion and metal contamination in thin polycide gate conductor of mosfet device  
A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N-...
5918132 Method for narrow space formation and self-aligned channel implant  
A method of forming a narrow space using a litho-less process is disclosed. A first mask is formed on a substrate, the first mask having an edge. A spacer is then formed adjacent to the edge. A...
5911111 Polysilicon polish for patterning improvement  
A polishing process for polysilicon gate patterning improvement using standard patterning techniques in the manufacture of high performance metal oxide semiconductor (MOS) devices. The addition of...
5908311 Method for forming a mixed-signal CMOS circuit that includes non-volatile memory cells  
A CMOS device that includes three-volt MOS transistor, five-volt MOS transistors, FLASH EPROM cells, poly resistors, and double-poly capacitors is formed in a single integrated CMOS process flow....
5906912 Processes for forming resist pattern and for producing semiconductor device  
An electroconductive pattern is formed by coating a substrate with a solution comprising 100 parts by weight of a soluble electroconductive polymer containing an organic radical capable of...
5904533 Metal salicide-CMP-metal salicide semiconductor process  
A metal salicide-CMP-metal salicide semiconductor process, suitable for a semiconductor substrate on which gates, sources (drains), spacers, and field oxides are formed. A first metal layer is...
5895246 Method of making semiconductor device with air gap between the gate electrode and substrate during processing  
A semiconductor device includes a semiconductor substrate of a first conductivity type having an active region and an inactive region, a gate electrode formed on the semiconductor substrate over...
5891783 Method of reducing fringe capacitance  
A method of reducing the fringe capacitance between a gate and a substrate in a semiconductor device. A silicon nitride is formed over a substrate with a buffer oxide layer thereon and patterned to...
5885888 Etching material and etching process  
An etching material comprising at least phosphoric acid, acetic acid, and nitric acid, with chromic acid added therein. Also claimed is an etching process using the etching material above, provided...
5879975 Heat treating nitrogen implanted gate electrode layer for improved gate electrode etch profile  
The etch profile of side surfaces of a gate electrode is improved by heat treating the gate electrode layer after nitrogen implantation and before etching to form the gate electrode. Nitrogen...
5879994 Self-aligned method of fabricating terrace gate DMOS transistor  
An active mask is used to etch field oxide in active areas down to an n- epitaxial substrate. After gate oxide growth, a polysilicon layer is deposited and planarized. The active mask defines the...
5880015 Method of producing stepped wall interconnects and gates  
A method is provided for making conductive structures whereby an insulating layer is formed over a substrate. A conductive layer is then formed over the insulating layer. A first photoresist layer...
5880008 Method for forming field oxide film  
A method for forming a field oxide film includes the steps of: (i) laminating a gate insulating film, a polysilicon layer and a first silicon nitride film over the entire surface of a semiconductor...
5877073 Modified poly-buffered locos forming technology avoiding the positive charge trapping at the beak of field oxide  
A method for fabrication of modified poly-buffered LOCOS without positive charges trapping at the beak of the field oxide. The method employs DIW (Deionized Water) to be sprayed onto the wafer...
5866473 Method of manufacturing a polysilicon gate having a dimension below the photolithography limitation  
A method of manufacturing an MOS transistor having a gate length dimension less than the dimension available by methods available with conventional manufacturing methods that are limited by optical...
5858865 Method of forming contact plugs  
Within an integrated circuit, a contact plug with a height not extending above the level of the gate/wordline nitride is nonetheless provided with a relatively large contact area or landing pad,...
5846871 Integrated circuit fabrication  
Undesirable counter doping of n + /p + gates illustratively through cross diffusion through an overlying silicide is inhibited by insertion of layers of titanium nitride and titanium, tungsten...
5843835 Damage free gate dielectric process during gate electrode plasma etching  
In a CMOS device uses a thin oxide film as a gate dielectric film, gate electrode plasma etching frequently induces gate dielectric damage. This invention discloses a process which can form a...
5843812 Method of making a PMOSFET in a semiconductor device  
An improved p+ polysilicon gated PMOSFET having a channel on the surface of a silicon substrate and improved short channel behavior is disclosed. A simplified process allows making a p+ doped gate...
5843827 Method of reducing dielectric damage from plasma etch charging  
A method of suppressing damage to gate dielectrics by reducing the electrical field across the gate dielectric during plasma etching, photoresist stripping, or plasma assisted deposition of the...
5840611 Process for making a semiconductor MOS transistor  
The present invention provides a process for forming an MOS semiconductor device having an LDD structure, which includes a forming a gate electrode by first etching a conductive layer to a certain...
5830776 Method of manufacturing thin film transistor  
A terminal section for anodic oxidation made of a metal which is the same kind of a metal as a light shielding film is formed on an end of a light transmitting substrate. Then, wiring space for the...
5827762 Method for forming buried interconnect structue having stability at high temperatures  
A buried interconnect structure which is stable at the high temperatures involved in BiCMOS, bipolar, and CMOS transistor process flows, and a method of making the same. The interconnect structure...
5824596 POCl.sub.3 process flow for doping polysilicon without forming oxide pillars or gate oxide shorts  
In a method of introducing phosphorous from phosphorous oxychloride (POCl 3 ) into an undoped gate polysilicon region formed as part of an integrated circuit structure, an initial MOS structure is...
5821172 Oxynitride GTE dielectrics using NH.sub.3 gas  
A semiconductor manufacturing process in which a single crystal silicon semiconductor substrate is immersed in an oxidation chamber maintained at a first temperature preferably between 400° and...
5811339 Method of fabricating deep submicron MOSFET with narrow gate length using thermal oxidation of polysilicon  
The present invention relates to forming a narrow gate MOSFET having a local ion implantation to reduce the junction capacitance. A polysilicon layer is formed over a semiconductor substrate. An...
5808348 Non-uniformly nitrided gate oxide and method  
A semiconductor device which includes a polysilicon gate separated from a semiconductor substrate by a re-oxidized nitrided oxide film in which the concentration of re-oxidized nitride in the film...
5804474 Method for forming a V-shaped gate electrode in a semiconductor device, and the structure of the electrode  
A method for forming a V-shaped gate electrode on a semiconductor substrate includes the following steps: A first gate opening is formed in a first resist between a source and a drain formed on a...
5801088 Method of forming a gate electrode for an IGFET  
A method of forming a gate electrode for an insulated-gate field-effect transistor (IGFET) is disclosed. The method includes forming a gate material for providing a gate electrode over a...
Matches 701 - 750 out of 868 < 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 >