Matches 651 - 700 out of 868 < 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 >
Match Document Document Title
6103582 Method to suppress boron penetration in P+ mosfets  
With the growing practice of doping gates for MOSFETs with boron, problems have been encountered due to later diffusion of the boron into the active region. To block this, argon ions are implanted...
6103632 In situ Etching of inorganic dielectric anti-reflective coating from a substrate  
The present invention is embodied in a method and apparatus for etching dielectric layers and inorganic ARC's without the need for removing the substrate being processed from the processing chamber...
6103605 Process for defining the width of silicon gates using spacers as an etch hard mask  
Process for controllably defining the width of silicon gates to critical dimensions. The process includes steps of first providing a semiconductor substrate (e.g. a silicon wafer) with a gate oxide...
6103559 Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication  
A method is provided for fabricating a semiconductor device, the method including forming a first dielectric layer above a structure and forming an island of a sacrificial layer above the first...
6103608 Method of forming a contact window  
The present invention discloses a method of forming a contact window on a substrate. The method in the present invention includes a step of forming a gate structure on said substrate having a gate...
6100147 Method for manufacturing a high performance transistor with self-aligned dopant profile  
A process for manufacturing a high performance transistor with self-aligned dopant profile. The process involves forming a source/drain mask pattern on a substrate. With a first implant material,...
6100142 Method of fabricating sub-quarter-micron salicide polysilicon  
A method of fabricating a semiconductor device using a Salicide process to increase the surface area of a polysilicon gate is described. First, a polysilicon layer is formed over a substrate. A...
6100140 Manufacturing method of semiconductor device  
A manufacturing method of a vertical type MOSFET, which can suppress vaporization of impurity from a semiconductor substrate and prevent variation in carrier density of the channel, is disclosed....
6100120 Method of locally forming a high-k dielectric gate insulator  
A method of forming a dielectric gate insulator in a transistor is disclosed herein. The method includes depositing a layer of material over a semiconductor structure; depositing a covering layer...
6093628 Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application  
A method for fabricating a deep sub-micron gate electrode, comprising polysilicon and metal, having ultra-low sheet resistance. The process begins by forming shallow trench isolation regions 14 in...
6093590 Method of fabricating transistor having a metal gate and a gate dielectric layer with a high dielectric constant  
A method of fabricating a transistor. A first dielectric layer with a high dielectric constant is formed on a substrate. An oxide layer is formed on the first dielectric layer. A silicon nitride...
6090676 Process for making high performance MOSFET with scaled gate electrode thickness  
A process for making a high performance MOSFET with a scaled gate electrode thickness. In one embodiment, the process comprises first providing a substrate. A gate dielectric layer is formed on the...
6090672 Ultra short channel damascene MOS transistors  
This invention is a damascene processing method for forming ultra short channel MOS transistors, where the channel length is not determined by photolithography. The method uses chemical mechanical...
6090692 Fabrication method for semiconductor memory device  
A fabrication method for a semiconductor memory device includes the steps of forming a gate pattern on a semiconductor substrate; forming first and second sidewall spacers at sides of the gate...
6087238 Semiconductor device having reduced-width polysilicon gate and non-oxidizing barrier layer and method of manufacture thereof  
A semiconductor device having a reduced polysilicon gate electrode width is provided along with a process for manufacturing such a device. In accordance with the present invention, a semiconductor...
6087249 Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation  
An integrated circuit transistor is provided having a gate oxide and a gate conductor arranged upon a semiconductor topography, the gate oxide and gate conductor are formed within a common chamber....
6083816 Semiconductor device and method of manufacturing the same  
A gate dielectric film 102, gates 104a formed of polysilicon, an offset oxidation film 106a formed of silicon nitride, and an etching stopper nitride film 108a formed of silicon nitride are...
6083815 Method of gate etching with thin gate oxide  
A method for etching polysilicon or polycide gate electrodes over thin gate oxides is described wherein the problem of pitting and trenching of the silicon beneath the gate oxide, caused by...
6080624 Nonvolatile semiconductor memory and method for manufacturing the same  
The present invention is directed to a flash EEPROM in which a plurality of resist patterns are arranged like an island such that only an interlayer insulation film formed on a field oxide film is...
6077776 Polysilicon residue free process by thermal treatment  
A new method of removing impurities and moisture from the surface of a wafer and thereby preventing polysilicon residue is described. A dielectric layer is provided over the surface of a...
6077733 Method of manufacturing self-aligned T-shaped gate through dual damascene  
A new method is provided to manufacture a T-shaped gate. A layer of insulation is deposited over a semiconductor surface (typically the surface of a substrate), a dual damascene structure...
6072213 Transistor having an etchant-scalable channel length and method of making same  
An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length. First and second masks are formed upon a conductive gate layer, wherein the...
6066533 MOS transistor with dual metal gate structure  
A method for making a ULSI MOSFET includes depositing a high-k gate insulator on a silicon substrate and then depositing a field oxide layer over the gate insulator. The field oxide layer is masked...
6063698 Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits  
A method for forming a gate dielectric (14b) begins by providing a substrate (12). A high K dielectric layer (14a) is deposited overlying the substrate (12). The dielectric layer (14a) contains...
6060376 Integrated etch process for polysilicon/metal gate  
A gate region of a transistor is prepared for receiving a deposit of metal. A chemical mechanical polishing process is performed to reduce thickness of an insulation layer above the gate region. At...
6060375 Process for forming re-entrant geometry for gate electrode of integrated circuit structure  
A crystalline semiconductor gate electrode having a re-entrant geometry and a process for making same are disclosed. The novel gate electrode may be formed from a polysilicon layer on a substrate...
6060377 Method for fabricating a polysilicon structure with reduced length that is beyond photolithography limitations  
A polysilicon structure is fabricated with a reduced length that is beyond that achievable from photolithography by using a silicidation anneal to control the reduced length. Generally, the present...
6057217 Process for production of semiconductor device with foreign element introduced into silicon dioxide film  
A MOS field effect transistor (MOSFET) comprising a semiconductor substrate 11 having thereon a gate silicon dioxide film 12 and a gate electrode 13 both formed by patterning, wherein in only at...
6057218 Method for simultaneously manufacturing poly gate and polycide gate  
The present invention discloses a method for simultaneously manufacturing a poly gate and a polycide gate which requires only one gate oxide layer deposition and one polysilicon layer deposition...
6051486 Method and structure for replaceable gate electrode in insulated gate field effect transistors  
A method and structure are provided for an IGFET which has a replaceable gate electrode fabrication and dual polished fabrication technique to simultaneously form source, drain and gate regions....
6051487 Semiconductor device fabrication using a sacrificial plug for defining a region for a gate electrode  
A semiconductor device is formed by forming a sacrificial plug over a substrate and forming active regions in the substrate adjacent the sacrificial plug. A film is then formed over portions of the...
6037233 Metal-encapsulated polysilicon gate and interconnect  
Provided are methods of forming a metal layer on the horizontal and vertical surfaces of a polysilicon gate electrode/interconnect in a MOS transistor, and devices having metal-encapsulated gates...
6037017 Method for formation of multilayer film  
A method for forming a multilayer film by introducing a material gas into a reduced-pressure reaction chamber provided with a pair of parallel planer electrodes and supplying a high-frequency...
6033975 Implant screen and method  
A semiconductor device (60) may comprise a semiconductor layer (12) having an outer surface (20). A plurality of gates (18) may be disposed over the outer surface (20) of the semiconductor layer...
6030874 Doped polysilicon to retard boron diffusion into and through thin gate dielectrics  
An embodiment of the instant invention is a method of fabricating a semiconductor device which includes a dielectric layer situated between a conductive structure and a semiconductor substrate, the...
6028005 Methods for reducing electric fields during the fabrication of integrated circuit devices  
A method for fabricating an integrated circuit device includes the steps of forming first and second conductive regions on a substrate. The second conductive region is divided into first and second...
6025253 Differential poly-edge oxidation for stable SRAM cells  
An SRAM cell having improved stability includes pass transistors having gate electrodes which are shaped by oxidation so that the lower edges of the gate electrodes are raised away from the...
6022815 Method of fabricating next-to-minimum-size transistor gate using mask-edge gate definition technique  
A method of fabricating minimum size and next-to-minimum size electrically conductive members using a litho-less process is disclosed. A substrate is provided, and a layer of gate dielectric...
6017808 Nitrogen implanted polysilicon gate for MOSFET gate oxide hardening  
A method for hardening of gate oxide without forming low dopant concentration regions at the gate oxide-polysilicon interface is described. Polysilicon is deposited onto gate oxide followed by...
6017809 Method of manufacturing semiconductor device  
A method of manufacturing a semiconductor device comprises the steps of forming a gate insulating film and a first silicon film on a semiconductor substrate, forming on the first silicon film a...
6015746 Method of fabricating semiconductor device with a gate-side air-gap structure  
A method of fabricating a semiconductor device. On a semiconductor substrate comprising a device isolation structure and an active region isolated by the device isolation region, an oxide layer is...
6015727 Damascene formation of borderless contact MOS transistors  
This invention is a processing method for forming MOS transistors. The method uses chemical mechanical polishing to self align an MOS transistor gate electrode to the channel region in both the...
6008518 Transistor and method of manufacturing the same  
A transistor and a fabrication method thereof, and in particular, a technique for compatibly improving reduction of an ON-state voltage and reduction of a turn-off time. First and second emitter...
6008100 Metal-oxide semiconductor field effect transistor device fabrication process  
A method of fabricating a MOS FET is provided. An oxide layer and a polysilicon layer are successively formed on the semiconductor substrate. A pyramidical photoresist layer is used as a mask for...
6008096 Ultra short transistor fabrication method  
A semiconductor process in which the transistor channel is defined by opposing sidewalls of a pair of masking structures formed on an upper surface of a semiconductor substrate. The spacing between...
6004853 Method to improve uniformity and the critical dimensions of a DRAM gate structure  
A process for fabricating a straight walled, silicon nitride capped, gate structure, for a MOSFET device, has been developed. The process features the creation of a straight walled, photoresist...
6001716 Fabricating method of a metal gate  
A method of fabricating a metal gate includes forming a gate insulating layer on a provided substrate, forming a PVD titanium nitride layer on the gate insulating layer, forming a CVD titanium...
5998285 Self-aligned T-shaped process for deep submicron Si MOSFET's fabrication  
A process is disclosed for the fabrication of a MOS device with a T-shaped gate electrode, in which a selective CVD technique has been utilized to simplify the T-shaped gate process. After the...
5981363 Method and apparatus for high performance transistor devices  
The present invention is directed to a method for forming a semiconductor device having a reduced channel length. The method comprises forming a layer of a dielectric material above a surface of a...
5981365 Stacked poly-oxide-poly gate for improved silicide formation  
A method of fabricating an integrated circuit transistor in a substrate is provided. A gate electrode stack is formed on the substrate. The stack has a first insulating layer, a first conductor...
Matches 651 - 700 out of 868 < 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 >