Matches 501 - 550 out of 864 < 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 >
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6362085 Method for reducing gate oxide effective thickness and leakage current  
A process for forming a nitrogen enriched ultra thin gate oxide is described. The nitrogen enrichment increases the dielectric constant of the gate oxide thereby decreasing it's effective oxide...
6362074 Integrated circuit processing with improved gate electrode fabrication  
An integrated circuit is fabricated with a layer of polysilicon located on top of shallow trench regions. The polysilicon is patterned so that the trench features are not exposed during an etching...
6362117 Method of making integrated circuit with closely spaced components  
An integrated circuit ( 10, 60, 110, 210 ) is fabricated according to a method which includes the steps of providing a structure ( 12, 112, 212 ) having a top surface ( 13, 113, 213 ), and forming...
6358827 Method of forming a squared-off, vertically oriented polysilicon spacer gate  
A method is taught for forming a rectangular or near rectangular polysilicon sidewall structure, which can be used as an ultra narrow MOSFET gate electrode. The method employs the use a step on a...
6355546 Thermally grown protective oxide buffer layer for ARC removal  
A thermally grown oxide buffer layer is formed on a silicon layer prior to depositing an ARC thereon, thereby preventing damage to the silicon layer during ARC removal. Embodiments include...
6352939 Method for improving the electrical properties of a gate oxide  
A method for improving the electrical properties of a gate oxide is disclosed. The method includes the steps of providing a silicon wafer with a gate oxide formed thereon, providing a platinum...
6352913 Damascene process for MOSFET fabrication  
An improved MOSFET transistor is disclosed having a high dielectric constant gate dielectric and a metal gate electrode. With such a procedure, the known problems with polysilicon gate electrodes...
6352930 Bilayer anti-reflective coating and etch hard mask  
In the manufacture of sub-0.35 micron semiconductors using deep ultraviolet lithography, a bilayer of silicon dioxide on top of silicon oxynitride is used as bottom anti-reflective coating and an...
6340627 Method of making a doped silicon diffusion barrier region  
Methods and apparatus for forming word line stacks are comprised of a silicon diffusion barrier region, doped with oxygen or nitrogen, coupled between a bottom silicon layer and a conductor layer....
6339017 Hard mask for integrated circuit fabrication  
A method of manufacturing small structures or narrow structures on an ultra-large scale integrated circuit utilizes a hard mask. A mask layer can be deposited over a top surface of a material above...
6337254 Method of forming trench isolation structure with dummy active regions and overlying discriminately doped conduction layer  
A device isolation structure and a method thereof including a semiconductor substrate wherein a field isolation region including a plurality of dummy active regions and an active region are...
6335251 Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor  
A semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed is arranged to have a gate electrode which is formed on the surface of a silicon...
6329256 Self-aligned damascene gate formation with low gate resistance  
In order to form a self-aligned damascene gate which enables the resistance of the gate to be reduced, a thick layer of dielectric material is formed over a semiconductor substrate in which drain...
6329251 Microelectronic fabrication method employing self-aligned selectively deposited silicon layer  
Within a method for fabricating a microelectronic device there is first provided a silicon substrate. There is then formed upon the silicon substrate a first series of structures having a...
6326246 Method for manufacturing thin film transistor  
In a thin film transistor (TFT), a part of a surface or a whole surface of aluminum used as a gate electrode is covered by anodic oxide. In a process after anodization process, ultraviolet light is...
6326251 Method of making salicidation of source and drain regions with metal gate MOSFET  
A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A uniform...
6326290 Low resistance self aligned extended gate structure utilizing A T or Y shaped gate structure for high performance deep submicron FET  
Two alternate gate electrode structures are developed with expanded top portions of the gate electrode to maintain or reduce electrode effective sheet resistance improving high frequency...
6326288 CMOS compatible SOI process  
In a method for producing an integrated circuit using a CMOS process, in particular a HV CMOS process, components are formed within troughs of different depths and of a first conductivity type, in...
6323141 Method for forming anti-reflective coating layer with enhanced film thickness uniformity  
A method for forming a patterned reflective layer first employs a substrate. There is then formed over the substrate a blanket reflective layer. There is then formed upon the blanket reflective...
6323093 Process for fabricating a semiconductor device component by oxidizing a silicon hard mask  
A process for fabricating a semiconductor device includes the formation of a hard-mask using lithographic techniques, followed by an oxidation process to reduce the lateral dimension of the...
6319812 Method of manufacturing a semiconductor device  
Sintering is effected a gate insulating film of a transistor in a hydrogen atmosphere at a temperature from 450° C. to 600° C. only before formation of an interconnection layer such as an...
6319801 Method for cleaning a substrate and cleaning solution  
A method for cleaning a substrate having a patterned metal layer formed thereon includes the step of removing metallic contaminants from the substrate by use of an aqueous solution of carboxylic...
6319802 T-gate formation using modified damascene processing with two masks  
A method for fabricating a T-gate structure is provided. A structure is provided that has a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer and a sacrificial...
6313019 Y-gate formation using damascene processing  
A method for fabricating a Y-gate structure is provided. The method comprises the steps of providing a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer, a first...
6306741 Method of patterning gate electrodes with high K gate dielectrics  
A buffer layer and a gate dielectric layer overlying a substrate having at least one active area is provided. A sacrificial oxide layer is formed over the gate dielectric layer. A nitride layer is...
6306738 Modulation of gate polysilicon doping profile by sidewall implantation  
A device and method to modulate a gate polysilicon doping profile by performing a sidewall implantation. The method includes forming a gate on a substrate and implanting ions through a sidewall in...
6303481 Method for forming a gate insulating film for semiconductor devices  
A method for forming a gate insulating film for a semiconductor device comprising forming an insulating film of silicon nitride or silicon oxynitride in the active regions of the semiconductor...
6303494 Method of forming gate electrode in semiconductor device  
A method of forming a gate electrode in a semiconductor device which can effectively prevent abnormal oxidation of a metal layer without occurring thermal budget and the deterioration of a gate...
6303418 Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer  
A method of forming a metal gate structure, on a high k gate insulator layer, for NMOS devices, and simultaneously forming a metal-polysilicon gate structure, on the same high k gate insulator...
6300177 Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials  
A method of forming a gate electrode, comprising the following steps. A semiconductor substrate having an overlying patterned layer exposing a portion of the substrate within active area and...
6300199 Method of defining at least two different field effect transistor channel lengths using differently angled sidewall segments of a channel defining layer  
A method of defining at least two different field effect transistor channel lengths includes forming a channel defining layer over a substrate, the semiconductor substrate having a mean global...
6297111 Self-aligned channel transistor and method for making same  
A method for forming a transistor comprises the steps of: forming a gate stack on the surface of a semiconductor substrate; implanting a first dose of an impurity into the substrate at a sufficient...
6297107 High dielectric constant materials as gate dielectrics  
A semiconductor structure having a gate dielectric between a gate electrode and a semiconductor substrate is formed with a high dielectric metal oxide layer by replacing a sacrificial gate oxide....
6294447 Method of making devices having thin dielectric layers  
A method for making a thin dielectric layer is disclosed which is useful in fabricating semiconductor devices, particularly transistors and DRAM cell devices. The method comprises a two-steps,...
6291330 Method of fabricating gate structure to reduce stress production  
A fabrication method for a gate structure formed on a substrate, which has isolation structures formed therein. A buffer oxide layer is formed, followed by forming a patterned nitride layer and a...
6291365 Method for manufacturing thin gate silicon oxide layer  
In a method for manufacturing a semiconductor device where a silicon substrate is loaded in an oxidation furnace whose temperature is a first value, the temperature of the oxidation furnace is...
6291329 Protective oxide buffer layer for ARC removal  
An oxide buffer layer is formed between an underlying silicon layer and overlying ARC to prevent damage to the silicon layer when removing the ARC. Embodiments include depositing a silicon oxide...
6287904 Two step mask process to eliminate gate end cap shortening  
Metal oxide semiconductor devices are formed having gates with minimum endcap width and no source/drain leakage. A pair of source/drain regions is formed in a substrate, and a gate oxide is formed...
6287897 Gate dielectric with self forming diffusion barrier  
A method for forming a semiconductor device comprising forming a dielectric layer on an area of a silicon substrate; implanting nitrogen atoms into said dielectric layer; forming a conductive layer...
6287958 Method of manufacturing a self-aligned etch stop for polycrystalline silicon plugs on a semiconductor device  
A method for providing a self-aligned etch stop layer comprises the steps of providing a dielectric layer having a polycrystalline silicon (poly) plug formed therein. An aluminum layer is formed to...
6284633 Method for forming a tensile plasma enhanced nitride capping layer over a gate electrode  
A tPEN layer (108) having a tensile stress is formed over a conductive gate stack (104-106) provided on a semiconductor substrate. Following the formation of the conductive gate stack (104-106), an...
6284580 Method for manufacturing a MOS transistor having multi-layered gate oxide  
In a pretreatment process, a silicon oxide film (13) with nitrogen content is formed on a semiconductor substrate (10). In a segregation process executing heat treatment in an inert gas atmosphere,...
6284611 Method for salicide process using a titanium nitride barrier layer  
This invention provides a method for forming a self-aligned silicide with low sheet resistance in the N+ source and drain regions and the N+ polysilicon regions in a semiconductor device using a...
6284613 Method for forming a T-gate for better salicidation  
A method for a T-gate and salicide process that allows narrow bottom gate widths below 0.25 μm and wide top gate widths to allow silicide gate contacts on the top of the T-gate. A dummy gate...
6281100 Semiconductor processing methods  
In one aspect, the invention includes a semiconductor processing method comprising a) forming a metal silicide layer over a substrate; b) depositing a layer comprising silicon, nitrogen and oxygen...
6277719 Method for fabricating a low resistance Poly-Si/metal gate  
A method for forming a low resistance metal/polysilicon gate for use in CMOS devices comprising: (1) a novel anneal step prior to formation of a diffusion barrier layer and (2) a novel diffusion...
6277708 Semiconductor structures for suppressing gate oxide plasma charging damage and methods for making the same  
Disclosed is a semiconductor diode structure, and method for making semiconductor diode structures for suppressing transistor gate oxide plasma charging damage. The semiconductor diode structure...
6277718 Semiconductor device and method for fabricating the same  
The method for fabricating a semiconductor device comprises an insulation film forming step of forming an insulation film 12 on a semiconductor substrate 10, a semiconductor layer forming step of...
6274421 Method of making metal gate sub-micron MOS transistor  
A MOS transistor is formed on a single crystal silicon substrate doped to form a conductive layer of a first type, and includes: an active region formed on said substrate; a source region and a...
6270929 Damascene T-gate using a relacs flow  
A method for fabricating a T-gate structure is provided. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer and an insulating...
Matches 501 - 550 out of 864 < 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 >