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6468887 Semiconductor device and a method of manufacturing the same  
In a semiconductor device of this invention, a pillar projection serving as a very thin active region is formed on the surface of a p-type silicon semiconductor substrate. A gate electrode 21 is...
6468888 Method for forming polysilicon-germanium gate in CMOS transistor and device made thereby  
A method for making a ULSI MOSFET chip includes forming transistor gates on a substrate and a semiconductor device thereby made. The gates are formed by depositing a polysilicon layer on the...
6468877 Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner  
A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor substrate having at least a pair of STIs defining an active region is provided....
6461950 Semiconductor processing methods, semiconductor circuitry, and gate stacks  
In one aspect, the invention includes a semiconductor processing method comprising a) forming a metal silicide layer over a substrate; b) depositing a layer comprising silicon, nitrogen and oxygen...
6458641 Method for fabricating MOS transistors  
In PMOS having a gate electrode 7 of a p-type polysilicon film 5 along with a silicon nitride film 13, boron diffusion from the p-type polysilicon film 5 and boron punching through the gate...
6458717 Methods of forming ultra-thin buffer oxide layers for gate dielectrics  
A first option is a method of forming an ultra thin buffer oxide layer comprises the following steps. A silicon substrate having STI regions formed therein separating at least one active area is...
6458664 Method for fabricating a field-effect transistor having an anti-punch-through implantation region  
A simple method for fabricating a field-effect transistor having an anti-punch-through implantation region is provided. After the anti-punch-through implantation region is formed, a semiconductor...
6455405 Using implantation method to control gate oxide thickness on dual oxide semiconductor devices  
A method for forming dual thickness gate oxide layers comprising the following steps. A structure having at least a first area and a second area is provided. The second area of the structure is...
6451657 Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant  
A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a...
6451677 Plasma-enhanced chemical vapor deposition of a nucleation layer in a tungsten metallization process  
An embodiment of the instant invention is a method of fabricating an electronic device formed over a semiconductor substrate and having a conductive feature comprised of tungsten, the method...
6448164 Dark field image reversal for gate or line patterning  
A method of forming either a gate pattern or a line pattern in a resist by using a dark field mask and a combination of a negative photoresist and a positive photoresist. The dark field mask is...
6448165 Method for controlling the amount of trim of a gate structure of a field effect transistor  
For fabricating a field effect transistor within an active device area of a semiconductor substrate, a layer of gate dielectric material is deposited on the semiconductor substrate. A layer of gate...
6448163 Method for fabricating T-shaped transistor gate  
A method of forming a T-shaped gate for a transistor, comprising: defining a base length of the gate by forming a gate stack on a substrate; defining a contact length by forming a layer of nitride...
6448127 Process for formation of ultra-thin base oxide in high k/oxide stack gate dielectrics of mosfets  
A method and article of manufacture of an ultra-thin base oxide or nitrided oxide layer in a CMOS device. The method and article of manufacture are formed by providing a silicon wafer with an...
6448166 Method for forming a gate for semiconductor devices  
The present invention discloses a method for forming a gate for semiconductor devices by depositing a TaO x N y film as a gate oxide film. The method includes the steps of providing a...
6440783 Method for fabricating a thin film transistor display  
A thin film transistor display is formed on a substrate having a first region and a second region. The first region includes a transistor area, and the second region includes a pad area. A gate...
6436764 Method for manufacturing a flash memory with split gate cells  
A method for forming self-aligned split gates in a flesh memory is disclosed. The method includes two-step lithographic definition of a split gate and nitride spacer formation of the gate. The...
6436775 MOSFET device fabrication method capable of allowing application of self-aligned contact process while maintaining metal gate to have uniform thickness  
The MOSFET fabrication method allows application of a self-aligned contact (SAC) process while maintaining a metal gate, such as a tungsten gate, to have a uniform thickness. The process involves...
6436746 Transistor having an improved gate structure and method of construction  
A method of fabricating an improved gate structure that may be used in a transistor. A primary insulation layer ( 22 ) may be formed adjacent a substrate ( 12 ). A disposable gate ( 24 ) may be...
6432801 Gate electrode in a semiconductor device and method for forming thereof  
The present invention relates to a method for forming a gate electrode in a semiconductor device, which can improve GOI characteristics and allows for an effective suppression of metal silicide...
6432809 Method for improved passive thermal flow in silicon on insulator devices  
Increased heat dissipation is provided in a high performance integrated circuit by providing a thermally conductive path from a thermal poly plug (TPP) which extends through a thermal barrier in...
6429060 Method for fabricating semiconductor device  
The accuracy in forming a gate electrode or an interconnect is improved by using a dummy gate electrode or a dummy interconnect. In addition, the dummy gate electrode or the dummy interconnect is...
6429110 MOSFET with both elevated source-drain and metal gate and fabricating method  
A method of forming a transistor and a semiconductor-metal-oxide transistor. The method at least includes provides a substrate; covers the substrate by a doped amorphous polysilicon layer and a...
6429109 Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate  
A method of forming a gate comprising the following steps. A substrate is provided. A pre-gate structure is formed over the substrate. The pregate structure includes a sacrificial metal layer...
6423633 Method for manufacturing diffusion barrier layer  
A method for manufacturing a diffusion barrier layer over a substrate having a patterned copper layer. A refractory metal layer is formed on the substrate and a top surface and a sidewall of the...
6420280 Method and system for reducing ARC layer removal by providing a capping layer for the ARC layer  
A method and system for providing a semiconductor device is disclosed. The method and system include depositing an antireflective coating (ARC) layer having antireflective properties. The method...
6420248 Double gate oxide layer method of manufacture  
A method of manufacturing a double gate oxide layer. A substrate has trenches that divide the substrate into a memory circuit region and a logic circuit region. A dielectric layer is formed on the...
6420237 Method of manufacturing twin bit cell flash memory device  
The present invention provides a twin bit cell flash memory device and its fabricating method. The method is to first form a gate oxide layer on the surface of the silicon substrate followed by...
6417104 Method for making a low resistivity electrode having a near noble metal  
A method for forming conductive lines such as interconnects and DRAM gate stacks. A blanket stack is formed on a substrate including a conductive diffusion barrier, a near noble metal such as...
6417084 T-gate formation using a modified conventional poly process  
A method is provided for fabricating a T-gate structure. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer, and an ARC layer...
6417082 Semiconductor structure  
A process for making a semiconductor structure comprises implanting nitrogen through a layer comprising SiO 2 into a substrate comprising Si, wherein the layer is on the substrate, and wherein the...
6406950 Definition of small damascene metal gates using reverse through approach  
Various methods of fabricating circuit devices incorporating a gate stack are disclosed. In one aspect, a method of fabricating a circuit device on a substrate is provided that includes forming a...
6399466 Method of manufacturing non-volatile semiconductor memory device storing charge in gate insulating layer therein  
A method of manufacturing a non-volatile semiconductor memory device having a gate insulating layer composed of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide...
6399431 ESD protection device for SOI technology  
A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. A silicon-on-insulator substrate is provided comprising a semiconductor substrate...
6391751 Method for forming vertical profile of polysilicon gate electrodes  
The present invention is directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of polysilicon, forming a masking layer above...
6391753 Process for forming gate conductors  
An ultra-large-scale integrated (ULSI) circuit includes MOSFETs. The MOSFETs can include a gate structure manufactured by utilizing a spacer structure as a mask. The spacer structure can be silicon...
6391752 Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane  
A method of fabricating a SOI semiconductor device with an implanted ground plane in the silicon substrate to increase the doping concentration underneath the channel region for suppressing...
6387760 Method for making semiconductor device having bent gate electrode  
A semiconductor device comprising, on a semiconductor substrate, an element-isolating region, an active region, and a gate electrode with a bent portion having a bent-angle θ on the active region....
6387785 Lithography and etching process  
A lithography and etching process, which is applicable on a substrate, is described. A material layer to be patterned is formed on the substrate, then a silicon oxynitride layer of more than 800...
6387739 Method and improved SOI body contact structure for transistors  
Disclosed is process for maufacture of a type “BC” body contacted SOI transistor with a process for making these transistors in a manufacturing environment to providing a structure which...
6387784 Method to reduce polysilicon depletion in MOS transistors  
A method is provided to reduce poly depletion in MOS transistors. Conventionally, after a polysilicon electrode has been doped, an anneal step is usually performed to activate the dopants. However,...
6383876 MOS device having non-uniform dopant concentration and method for fabricating the same  
A metal-oxide-semiconductor (MOS) device in which the nonuniform dopant concentration in the channel region is obtained by means of ion implantation through a polysilicon gate electrode of...
6380055 Dopant diffusion-retarding barrier region formed within polysilicon gate layer  
A diffusion-retarding barrier region is incorporated into the gate electrode to reduce the downward diffusion of dopant toward the gate dielectric. The barrier region is a nitrogen-containing...
6376347 Method of making gate wiring layer over semiconductor substrate  
Disclosed is a method of making a gate wiring layer, in which a carbon-based layer is patterned by dry etching using a gas that does not etch a gate insulating layer so as to form a gate wiring...
6376319 Process to fabricate a source-drain extension  
A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been...
6373111 Work function tuning for MOSFET gate electrodes  
Insulated gate field effect transistors having gate electrodes with at least two layers of materials provide gate electrode work function values that are similar to those of doped polysilicon,...
6368948 Method of forming capped copper interconnects with reduced hillocks  
Reliably capped Cu interconnects are formed with a significant reduction in the amount and size of hillocks by reducing the time during which the Cu interconnect is exposed to elevated temperatures...
6365474 Method of fabricating an integrated circuit  
A transistor ( 12 ) and method of making an integrated circuit ( 10 ) uses a chromium based sacrificial gate ( 22 A) to align, dope and activate source and drain portions ( 36, 38, 52, 53, ) of the...
6365496 Elimination of junction spiking using soft sputter etch and two step tin film during the contact barrier deposition process  
A contact opening to a silicon substrate within which a metal contact is to be formed is cleaned by soft sputter etch to clean the substrate surface and remove any residue which would interfere...
6362057 Method for forming a semiconductor device  
A conductive layer ( 14 ) and a dummy feature ( 16 ) are formed over a semiconductor substrate ( 10 ) doped with a first dopant type. A spacer ( 42 ) is then formed adjacent the dummy feature ( 16...
Matches 451 - 500 out of 864 < 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 >