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7235468 FinFET device with reduced DIBL  
FinFET devices formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and methods for producing the same. The methods involve dopant...
7144751 Back-contact solar cells and methods for fabrication  
Methods for fabrication of emitter wrap through (EWT) back-contact solar cells and cells made by such methods. Certain methods provide for higher concentration of dopant in conductive vias compared...
7115476 Semiconductor manufacturing method and semiconductor device  
A method of manufacturing a semiconductor device includes forming a mask layer on a semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a...
7105411 Methods of forming a transistor gate  
A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate...
7078315 Method for eliminating inverse narrow width effects in the fabrication of DRAM device  
The present invention provides a method for eliminating inverse narrow width effects in the fabrication of DRAM devices. A semiconductor substrate is provided having thereon a shallow trench. The...
7022576 Method of manufacturing a semiconductor device  
The present invention relates to a method of manufacturing a semiconductor device. According to the present invention, a sidewall layer containing impurities is formed on a part of gate electrode,...
6995061 Multi-bit stacked-type non-volatile memory and manufacture method thereof  
The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a...
6924200 Methods using disposable and permanent films for diffusion and implantation doping  
Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and...
6903025 Method of purging semiconductor manufacturing apparatus and method of manufacturing semiconductor device  
A method of purging a semiconductor manufacturing apparatus comprises a step of etching a CVD-deposited film deposited in a chamber constituting a semiconductor manufacturing apparatus which has...
6890825 Method for controlling dopant profiles and dopant activation by electron beam processing  
An improved dopant application system and method for the manufacture of microelectronic devices accurately places dopant on and within a dielectric or semiconductor surface. Diffusing and...
6849529 Deep-trench capacitor with hemispherical grain silicon surface and method for making the same  
A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench,...
6828214 Semiconductor member manufacturing method and semiconductor device manufacturing method  
This invention provides an SOI substrate manufacturing method using a transfer method (bonding and separation). A separation layer ( 12 ) is formed on a silicon substrate ( 11 ). A silicon layer (...
6806173 Method for producing highly doped semiconductor components  
A method is proposed for producing semiconductor components, in which at least one doped region is introduced in a wafer, a solid glass layer provided with dopant being applied on at least one of...
6746907 Methods of forming field effect transistors and field effect transistor circuitry  
Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a...
6737342 Composite spacer scheme with low overlapped parasitic capacitance  
A method and composition for a composite spacer with low overlapped capacitance includes a low-k dielectric spacer layer. A first spacer is deposited on a partially formed semiconductor device...
6723587 Ultra small-sized SOI MOSFET and method of fabricating the same  
An ultra small-sized SOI MOSFET having a high integration density, low power consumption, but high performances, and a method of fabricating the same are provided. The method includes preparing a...
6696354 Method of forming salicide  
A method of forming a salicide. A metal layer is formed on a silicon-based substrate comprising a gate with a spacer on the side wall of the gate and a source/drain is provided. Next, a first...
6649542 Multi-level type nonvolatile semiconductor memory device  
A method of writing data into a memory cell of a non-volatile semiconductor memory device includes setting a write voltage applied to portions of the memory cells depending upon a value of write...
6607966 Selective method to form roughened silicon  
A method of forming silicon storage nodes on silicon substrates, wherein the silicon storage nodes have a roughened surface, which does not result in deposition of silicon atoms over the entire...
6593196 Methods of forming a transistor gate  
A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate...
6566212 Method of fabricating an integrated circuit with ultra-shallow source/drain extensions  
A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a solid-phase impurity source. The solid-phase impurity source can be a doped silicon dioxide layer...
6524880 Solar cell and method for fabricating the same  
A technique for fabricating a solar cell includes an n + emitter region first being formed on a front surface of the cell, and then front and rear insulating layers being formed on both sides of...
6506653 Method using disposable and permanent films for diffusion and implant doping  
Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and...
6498079 Method for selective source diffusion  
Deep profile and highly doped impurity regions can be formed by diffusing from a solid source or doped silicon glass and using a patterned nitride layer. An oxide etch stop and polysilicon...
6479352 Method of fabricating high voltage power MOSFET having low on-resistance  
Test structures for a high voltage MOSFET are provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate....
6448105 Method for doping one side of a semiconductor body  
A method for doping one side of a semiconductor substrate, such as in a silicon wafer, wherein an oxide layer is deposited on both the side to be doped and the non-doped side of the semiconductor...
6410410 Method of forming lightly doped regions in a semiconductor device  
A method is disclosed in which a lightly doped region in a semiconductor layer is obtained by diffusing dopant atoms of a first and second type into the underlying semiconductor layer. Preferably,...
6387758 Method of making vertical field effect transistor having channel length determined by the thickness of a layer of dummy material  
For fabricating a vertical field effect transistor on a semiconductor substrate, a bottom layer of doped insulating material is deposited on the semiconductor substrate. A layer of dummy material...
6380040 Prevention of dopant out-diffusion during silicidation and junction formation  
High integrity cobalt silicide contacts are formed with shallow source/drain junctions. Embodiments include depositing a layer of cobalt on a substrate above intended source/drain regions, followed...
6372589 Method of forming ultra-shallow source/drain extension by impurity diffusion from doped dielectric spacer  
A method of fabricating an integrated circuit (IC) with source and drain extension regions. Advantageously, the source and drain extension regions are formed without damage related to integrated...
6365493 Method for antimony and boron doping of spherical semiconductors  
A method for doping crystals is disclosed. The method includes a receiver for receiving semiconductor spheres and doping powder. The semiconductor spheres and dopant powder are then directed to a...
6362508 Triple layer pre-metal dielectric structure for CMOS memory devices  
A CMOS memory device includes source and drain regions diffused into a substrate, a polysilicon gate structure formed over a channel region located between the first and second diffusion regions,...
6355536 Selective method to form roughened silicon  
A method of forming silicon storage nodes on silicon substrates, wherein the silicon storage nodes have a roughened surface, which does not result in deposition of silicon atoms over the entire...
6348385 Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant  
The method for a transistor using a replacement gate process that has a doped low-K dielectric spacer that lowers the junction capacitance. A dummy gate is formed over a substrate. Ions are...
6303453 Method of manufacturing a semiconductor device comprising a MOS transistor  
The invention relates to a method of manufacturing a (horizontal) MOST, as used, for example, in (BI)CMOS ICs. On either side of a gate electrode (2), the surface of a silicon substrate (10, 11)...
6300228 Multiple precipitation doping process  
A multiple precipitation doping process for doping a semiconductor substrate (30) starts with forming an amorphous region (32) in the substrate (30). Through multiple laser exposures, multiple...
6297134 Deposition of titanium oxide film containing droping element on Si substrate  
A titanium oxide film containing a dopant element formed on a silicon substrate by supplying a titanium compound for forming the titanium oxide film and a compound of a dopant element for a silicon...
6291328 Opto-electronic device with self-aligned ohmic contact layer  
An opto-electronic device has a diffusion area of one conductive type formed in a semiconductor substrate of another conductive type, an ohmic contact layer making contact with the diffusion area,...
6284612 Process to fabricate ultra-short channel MOSFETs with self-aligned silicide contact  
The method of the present invention includes the following steps. First, a gate oxide layer is formed on the substrate. An undoped polysilicon layer is formed over the gate oxide layer. Then, a...
6274467 Dual work function gate conductors with self-aligned insulating cap  
A dual work function gate conductor with a self-aligned insulating cap and method for forming the same is provided. Two diffusion regions are formed in a substrate and a gate stack is formed over...
6255190 Method for dielectrically isolated deep pn-junctions in silicon substrates using deep trench sidewall predeposition technology  
A method for forming very deep pn-junctions without using epitaxy or extensively high temperature processing is provided. At least two parallel deep trenches are etched into a silicon substrate....
6248650 Self-aligned BJT emitter contact  
A bipolar transistor includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region. and a base link-up region within the...
6238985 Semiconductor device and method for fabricating the same  
A semiconductor device is disclosed, including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a first gate insulating layer formed between the gate electrode...
6221704 Process for fabricating short channel field effect transistor with a highly conductive gate  
Semiconductor devices are fabricated by providing a substrate; forming isolation regions in the substrate; forming a first insulating layer on the isolation regions and the substrate; forming a...
6218236 Method of forming a buried bitline in a vertical DRAM device  
A method of forming a shallow outdiffused buried bitline in a vertical semiconductor memory device is disclosed which utilizes annealing and oxidation to drive-in and pile-up the dopant atom into...
6207540 Method for manufacturing high performance MOSFET device with raised source and drain  
A MOSFET device and a method of manufacturing the device. The device has a trench formed in a silicon substrate. The channel of the device is at the bottom of the trench. Diffusion layers are...
6204158 Reduced diffusion of a mobile specie from a metal oxide ceramic into the substrate  
A scavenger layer is provided to prevent the diffusion of an excess mobile specie from a metal oxide ceramic into unwanted parts of a device. The scavenger layer is provided above the metal oxide...
6194280 Method for forming a self-aligned BJT emitter contact  
A bipolar transistor includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region, and a base link-up region within the...
6190979 Method for fabricating dual workfunction devices on a semiconductor substrate using counter-doping and gapfill  
A method for counter-doping gate stack conductors on a semiconductor substrate, which substrate is provided with narrow space array regions (i.e., memory device regions) having a plurality of...
6187642 Method and apparatus for making mosfet's with elevated source/drain extensions  
The inventive method provides improved semiconductor devices, such as MOSFET's with raised source/drain extensions on a substrate with isolation trenches etched into the surface of the substrate....
Matches 1 - 50 out of 252 1 2 3 4 5 6 >