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7629240 Controlling dopant diffusion in a semiconductor region  
Dopant diffusion into semiconductor material is controlled during fabrication of a semiconductor structure by depositing a nucleation layer over a first layer of the semiconductor structure and...
7625812 Silicon nano wires, semiconductor device including the same, and method of manufacturing the silicon nano wires  
A method of manufacturing silicon nano wires including forming microgrooves on a surface of a silicon substrate, forming a first doping layer doped with a first dopant on the silicon substrate and...
7615393 Methods of forming multi-doped junctions on a substrate  
A method of forming a multi-doped junction on a substrate is disclosed. The method includes providing the substrate doped with boron, the substrate including a first substrate surface with a first...
7611977 Process of phosphorus diffusion for manufacturing solar cell  
This invention discloses a process of phosphorus diffusion for manufacturing solar cell, comprising annealing a mono-crystalline silicon wafer in a nitrogen atmosphere at 900-950° C. for twenty to...
7608524 Method of and system for forming SiC crystals having spatially uniform doping impurities  
In a physical vapor transport method and system, a growth chamber charged with source material and a seed crystal in spaced relation is provided. At least one capsule having at least one capillary...
7605064 Selective laser annealing of semiconductor material  
A method of manufacture for semiconductor electronic products and a circuit structure. A semiconductor material has a surface region and dopant is provided to a portion of the surface region. The...
7605052 Method of forming an integrated circuit having a device wafer with a diffused doped backside layer  
A method for forming a diffused, doped backside layer on a device wafer oxide bonded to a handle wafer in an integrated circuit is provided. The method comprises forming a thermal bond oxide layer...
7564078 Tunable semiconductor component provided with a current barrier  
Semiconductor component or device is provided which includes a current barrier element and for which the impedance may be tuned (i.e. modified, changed, etc.) using a focused heating source.
7557023 Implantation of gate regions in semiconductor device fabrication  
A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and...
7550358 MEMS device including a laterally movable portion with piezo-resistive sensing elements and electrostatic actuating elements on trench side walls, and methods for producing the same  
A method to create piezoresistive sensing elements and electrostatic actuator elements on trench sidewalls is disclosed. P-type doped regions are formed in the upper surface of an n-type substrate....
7547618 System and method for providing a deep connection to a substrate or buried layer of a semiconductor device  
A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial...
7524745 Method and device for doping, diffusion and oxidation of silicon wafers under reduced pressure  
Method and device for doping or diffusion, or oxidation of silicon wafers ( 4 ), the wafers being introduced into the chamber ( 2 ) of an oven ( 1 ) wherein is introduced at least a gas for...
7514345 Electroactive polymers for lithography  
Systems and methods for lithography include actuating an electroactive polymer member to position mask and/or substrate.
7485555 Methods for forming a P-type polysilicon layer in a semiconductor device  
A P-type polysilicon layer having a stable and desired resistivity is formed by alternately depositing a plurality of silicon atom layers and a plurality of group IIIA element atom layers on a...
7452785 Method of fabrication of highly heat dissipative substrates  
The invention relates to a method for fabricating a composite structure having heat dissipation properties greater than a bulk single crystal silicon structure having the same dimensions. The...
7439159 Fusion bonding process and structure for fabricating silicon-on-insulator (SOI) semiconductor devices  
A method of fabricating a semiconductor-on-insulator device including: providing a first semiconductor wafer having an about 200 angstrom thick oxide layer thereover; etching the first...
7435514 Active mask lithography  
An active mask emits a patterned energy flux in response to an energy input.
7368356 Transistor with doped gate dielectric  
A transistor and method of manufacture thereof. A semiconductor workpiece is doped before depositing a gate dielectric material. Using a separate anneal process or during subsequent anneal...
7338876 Method for manufacturing a semiconductor device  
A method for forming a semiconductor memory device includes the steps of: implanting a dopant in a semiconductor substrate; heat treating the semiconductor substrate in an oxidizing ambient to...
7338829 Semiconductor structures having through-holes sealed with feed through metalization  
The invention relates to a method for producing a detector for determining the energy of photons and charged particles; to be precise, a so-called ΔE detector or transmission detector. The...
7262111 Method for providing a deep connection to a substrate or buried layer in a semiconductor device  
A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial...
7247548 Doping method and semiconductor device using the same  
The present invention achieves a shallow junction of a source and a drain, and provides a doping method which makes device properties reproducible and a semiconductor device fabricated using the...
7235468 FinFET device with reduced DIBL  
FinFET devices formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and methods for producing the same. The methods involve dopant...
7220674 Copper alloys for interconnections having improved electromigration characteristics and methods of making same  
Formation of copper alloy interconnect lines on integrated circuits includes introducing dopant elements into a copper layer. Copper alloy interconnect lines may be formed by providing a doping...
7202164 Method of forming ultra thin silicon oxynitride for gate dielectric applications  
A method of forming a gate dielectric layer is disclosed. The method comprises the following steps. A substrate is provided having silicon regions containing surfaces upon which gate dielectrics...
7170084 Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication  
An n-type MOSFET (NMOS) is implemented on a substrate having an epitaxial layer of strained silicon formed on a layer of silicon germanium. The MOSFET includes first halo regions formed in the...
7166232 Method for producing a solid body including a microstructure  
According to a method for producing a solid body ( 1 ) including a microstructure ( 2 ), the surface of a substrate ( 3 ) is provided with a masking layer ( 6 ) that is impermeable to a substance...
7122454 Method for improving nitrogen profile in plasma nitrided gate dielectric layers  
A method is provided wherein a gate dielectric film that is plasma nitrided in a chamber of one system is subsequently heated or “annealed” in another chamber of the same system. Processing...
7118997 Implantation of gate regions in semiconductor device fabrication  
A method for implanting gate regions essentially without implanting regions of the semiconductor layer where source/drain regions will be later formed. The method includes the steps of (a)...
7118998 Method of forming a conductive structure  
A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming a plurality of trenches...
7115437 Micromachined device having electrically isolated components and a method for making the same  
A micromachined structure having electrically isolated components is formed by thermomigrating a dopant through a substrate to form a doped region within the substrate. The doped region separates...
7112500 Thin film transistor, liquid crystal display and manufacturing method thereof  
The present invention provides a thin film transistor comprising a drain electrode and a source electrode separated by a channel region formed over a contact portion with an amorphous silicon layer...
7112484 Thin film diode integrated with chalcogenide memory cell  
An integrated programmable conductor memory cell and diode device in an integrated circuit comprises a diode and a glass electrolyte element, the glass electrolyte element having metal ions mixed...
7109087 Absorber layer for DSA processing  
A method of processing a substrate comprising depositing a layer comprising amorphous carbon on the substrate and then laser annealing the substrate is provided. Optionally, the layer further...
7109100 Semiconductor device and method for manufacturing semiconductor device  
To provide a semiconductor device able to be made uniform in diffusion depth of the impurity in a diffusion layer by a single diffusion and to give the desired threshold voltage and improved in...
7078315 Method for eliminating inverse narrow width effects in the fabrication of DRAM device  
The present invention provides a method for eliminating inverse narrow width effects in the fabrication of DRAM devices. A semiconductor substrate is provided having thereon a shallow trench. The...
7078325 Process for producing a doped semiconductor substrate  
A process is described which allows a buried, retrograde doping profile or a delta doping to be produced in a relatively simple and inexpensive way. The process uses individual process steps that...
7037815 Method for forming an ultra-shallow junction in a semiconductor substrate using a nuclear stopping layer  
A method for forming an ultra-shallow junction in a semiconductor substrate is provided. A semiconductor substrate having a top surface is prepared. A dielectric layer is then formed on the top...
7037814 Single mask control of doping levels  
In an integrated circuit, dopant concentration levels are adjusted by making use of a perforated mask. Doping levels for different regions across an integrated circuit can be differently defined by...
7029939 P-type semiconductor manufacturing method and semiconductor device  
A p-GaN layer 5 comprising materials such as a Group III nitride compound semiconductor is formed on a sapphire substrate 1 through MOVPE treatment, and a first metal layer 6 made of Co/Au is...
7026172 Reduced thickness variation in a material layer deposited in narrow and wide integrated circuit trenches  
A high density plasma chemical vapor deposition (HDP-CVD) process is used to deposit silicon dioxide in trenches of various widths. The thickness of the silicon dioxide filling both narrow and wide...
7026230 Method for fabricating a memory device  
The present invention is a method for fabricating a memory device. In one embodiment, an impurity concentration is created in a semiconductor substrate of a memory device. An annealing process is...
7005364 Method for manufacturing semiconductor device  
The invention provides a method for manufacturing a semiconductor device with which an impurity introduction region and a positioning mark region can be formed aligned, based on a common insulating...
6987054 Method of fabricating a semiconductor device having a groove formed in a resin layer  
A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer...
6974750 Process for forming a trench power MOS device suitable for large diameter wafers  
A process for fabricating power semiconductor devices involving preparation of a silicon wafer by epitaxial formation of an intrinsic silicon layer on a silicon substrate and high energy...
6936527 Low voltage non-volatile memory cell  
A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal...
6908803 Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures  
The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. The invention also...
6897132 Method of reducing the conductivity of a semiconductor and devices made thereby  
Disclosed is a method of reducing the conductivity/charge of a layer of group III-V semiconductor doped with Sn. The method includes the steps of: forming an region of SiO 2 on the semiconductor...
6872640 SOI CMOS device with reduced DIBL  
CMOS devices formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high...
6852623 Method for manufacturing zinc oxide semiconductors  
Disclosed herein is a method for manufacturing a zinc oxide semiconductor. The method comprises the steps of forming a zinc oxide thin film including a group V element as a dopant on a substrate by...
Matches 1 - 50 out of 227 1 2 3 4 5 >