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7550355 Low-leakage transistor and manufacturing method thereof  
A boron ion stream may be used to implant ions, such as boron ions, into the sidewalls of an active area, such as an NFET active area. The boron ion stream has both vertical tilt and horizontal...
7541260 Trench diffusion isolation in semiconductor devices  
A semiconductor structure is formed comprising a plurality of columns doped with alternating dopants. The columns are separated by trenches, and the dopant is diffused in the doped columns. The...
7422924 Image device and photodiode structure  
The invention provides a photodiode with an increased charge collection area, laterally spaced from an adjacent isolation region. Dopant ions of a first conductivity type with a first impurity...
7361540 Method of reducing noise disturbing a signal in an electronic device  
Certain aspects of a method for reducing noise disturbing at least one signal in an electronic device may comprise shielding a first layer doped with a first dopant from a signaling layer employing...
7279399 Method of forming isolated pocket in a semiconductor substrate  
A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms...
7235460 Method of forming active and isolation areas with split active patterning  
A process for forming isolation and active regions, wherein the patterning of an oxidation-barrier active stack is performed separately in the PMOS and NMOS regions. After the active stack is in...
7056816 Method for manufacturing semiconductor device  
A mask layer having an opening is formed on a semiconductor substrate. Next, oxygen ions and a first impurity are implanted into the semiconductor substrate using the mask layer as a mask. Then,...
6977204 Method for forming contact plug having double doping distribution in semiconductor device  
The present invention provides a method for forming a contact plug in a semiconductor device capable of preventing an increase of contact resistance caused by a decrease in dopant concentration and...
6908810 Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation  
A method of preventing decreasing threshold voltage of a MOS transistor by formation of shallow trench isolation. Shallow trenches are formed to isolate first active regions and second active...
6900091 Isolated complementary MOS devices in epi-less substrate  
An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the...
6846722 Method for isolating a hybrid device in an image sensor  
The present disclosure relates to a method for fabricating an image sensor capable of improving dark current characteristics. The method includes: forming sequentially a pad oxide layer and a pad...
6815287 Localized array threshold voltage implant to enhance charge storage within DRAM memory cells  
A DRAM device having improved charge storage capabilities and methods for providing the same. The device includes an array portion having a plurality of memory cells extending from a semiconductor...
6703187 Method of forming a self-aligned twin well structure with a single mask  
An improved method for forming a self-aligned twin well structure for use in a CMOS semiconductor device including providing a substrate for forming a twin well structure therein; forming an...
6696351 Semiconductor device having a selectively deposited conductive layer  
A process of production of a semiconductor memory device having a memory array including memory cells and a peripheral circuit on one substrate comprising the process of forming an interlayer...
6677223 Transistor with highly uniform threshold voltage  
Embodiments of the present invention relate to processes utilized in the manufacturing of a semiconductor device having transistors to achieve high uniformity of threshold voltages. The invention...
6660595 Implantation method for simultaneously implanting in one region and blocking the implant in another region  
A method of fabricating different transistor structures with the same mask. A masking layer ( 214 ) has two openings ( 204, 202 ) that expose two transistor areas ( 304,302 ). The width of the...
6472279 Method of manufacturing a channel stop implant in a semiconductor device  
The present invention provides a method of manufacturing a semiconductor device, and a related method manufacturing an integrated circuit. In one embodiment, the method of manufacturing a...
6362035 Channel stop ion implantation method for CMOS integrated circuits  
A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field...
6346464 Manufacturing method of semiconductor device  
A method of manufacturing a low power dissipation semiconductor power device is provided which is easy to perform and suitable for mass production. When a first and second conductivity-type regions...
6309921 Semiconductor device and method for fabricating semiconductor device  
The semiconductor device comprises a semiconductor substrate 10 of a first conduction-type, first wells 20a, 20b of a second conduction-type formed in a first region on the primary surface of the...
6268266 Method for forming enhanced FOX region of low voltage device in high voltage process  
A method for forming enhanced field oxide (FOX) region of low voltage devices in a high voltage process is disclosed. The method includes providing a semiconductor structure comprising a substrate,...
6133117 Method of forming trench isolation for high voltage device  
A trench isolation structure for high voltage device is provided including a high voltage well, a low voltage well, and trench oxide. The high voltage well is formed first to be the deep junction...
6121115 Methods of fabricating integrated circuit memory devices having wide and narrow channel stop layers  
An integrated circuit memory device includes a semiconductor substrate having a memory cell area and a select transistor area. A first field insulation layer is included in the memory cell area,...
6069059 Well-drive anneal technique using preplacement of nitride films for enhanced field isolation  
A method of forming an isolation structure comprising forming n-type areas and/or p-type areas implanted respectively therein on a first surface of the substrate. A pad oxide film is grown on the...
6054367 Ion implant of the moat encroachment region of a LOCOS field isolation to increase the radiation hardness  
A method of forming a semiconductor device and the device, the method comprising the steps of providing a silicon substrate of predetermined conductivity type having a layer of silicon oxide with a...
5981327 Method for forming wells of semiconductor device  
A method for forming wells of a semiconductor device, comprising the steps of forming a plurality of field insulating layers on a field region of a semiconductor substrate; forming first impurity...
5972753 Method of self-align cell edge implant to reduce leakage current and improve program speed in split-gate flash  
A method is provided for fabricating a self-aligned edge implanted split-gate flash memory comprising a semiconductor substrate of a first conductivity type having separated first and second...
5963820 Method for forming field oxide or other insulators during the formation of a semiconductor device  
A method for forming a semiconductor device comprises the steps of forming an oxide over a silicon layer, forming a blanket first nitride layer over the oxide layer and the silicon layer, and...
5963811 Method of fabricating a MOS device with a localized punchthrough stopper  
A method of fabricating a MOS device with a localized punchthrough stopper. In the process, a dummy layer is employed to define a well for implanting the localized punchthrough stopper. The dummy...
5927991 Method for forming triple well in semiconductor device  
An improved method for forming a triple well of a semiconductor device which is capable of more simply and easily forming a triple well without removing an anti-oxidation film. In addition, it is...
5895258 Semiconductor device fabrication method  
A semiconductor fabrication method for forming an insulation film and a first anti-oxidation film sequentially on a substrate which is sectioned into each of a peri region and a cell region. An...
5888873 Method of manufacturing short channel MOS devices  
Short channel MOS semiconductor devices are produced by implanting impurity ions through gate electrode and gate oxide layers, before patterning the gate electrode, using a composite mask of...
5830790 High voltage transistor of semiconductor memory devices  
The present invention relates to a high voltage transistor of a semiconductor memory device, and more particularly to a high voltage transistor which improves element isolation and breakdown...
5789287 Method of forming field isolation in manufacturing a semiconductor device  
This invention discloses a method of manufacturing a semiconductor device, especially a method of forming field isolation, in which a portion of an active region around a field oxide film is...
5786265 Methods of forming integrated semiconductor devices having improved channel-stop regions therein, and devices formed thereby  
Methods of forming semiconductor devices containing field oxide and channel-stop isolation regions therein include the steps of forming a plurality of first channel-stop isolation regions by...
5698458 Multiple well device and process of manufacture  
A method of manufacture of a semiconductor device comprises forming a silicon dioxide film upon the surface of said device, forming patterns of silicon nitride upon the surface of said silicon...
5688710 Method of fabricating a twin - well CMOS device  
A method of fabricating a twin-well integrated circuit device to implant the dopants directly through the nitride layer including steps of: The pad oxide layer and nitride layer are formed on a...
5688701 Method of making semiconductor device having a plurality of impurity layers  
A semiconductor device in which ability for isolating elements from each other can be improved and increase in substrate constant and junction capacitance can be suppressed, is disclosed. An...
5686348 Process for forming field isolation structure with minimized encroachment effect  
A method for minimizing the impurity encroachment effect of the field isolation structures for NMOS, PMOS and CMOS integrated circuits is disclosed. In the process, a first layer and a second layer...
5679588 Method for fabricating P-wells and N-wells having optimized field and active regions  
A method forms, in a CMOS semiconductor substrate, P- and N-wells having independently optimized field regions and active regions. In one embodiment, P- and N-wells are formed by (i) creating in...
5670395 Process for self-aligned twin wells without N-well and P-well height difference  
A method for forming self-aligned twin wells without height difference using only one masking step is described. A layer of silicon oxide is grown over the surface of a semiconductor substrate. A...
5633191 Process for minimizing encroachment effect of field isolation structure  
A method for minimizing the impurity encroachment effect of field isolation structures for NMOS, PMOS and CMOS integrated circuits is disclosed. In the process, a polysilicon layer is deposited on...
5624857 Process for fabricating double well regions in semiconductor devices  
A process for fabricating double well regions for a semiconductor device having a first well region of a first type and a second well region of a second type on the substrate is disclosed. The...
5614434 Method for minimizing the encroachment effect of field isolation structure  
A method for minimizing the impurity encroachment effect of field isolation structures for NMOS, PMOS and CMOS integrated circuits is disclosed. In the process, a sacrificial layer is deposited on...
5583062 Self-aligned twin well process having a SiO.sub.2 -polysilicon-SiO.sub.2 barrier mask  
A method is provided for forming planar, self aligned wells without a high temperature oxidation step to form an ion barrier. The method comprises preparing a substrate with a silicon...
5573963 Method of forming self-aligned twin tub CMOS devices  
The present invention provides a method of manufacturing twin wells in a silicon substrate which uses only one photo step and provides a smooth surface topology. The first embodiment begins by...
5525823 Manufacture of CMOS devices  
A method for forming field oxide regions on an integrated circuit device includes the steps of providing doped regions for formation of active devices. After the doped regions have been formed, a...
5523247 Method of fabricating self-aligned planarized well structures  
A method of forming a planarized self-aligned integrated circuit structure suitable for forming CMOS circuitry is provided. The method involves using first and second barrier layers to define the...
5500392 Planar process using common alignment marks for well implants  
A preferred embodiment of the present invention is a method of forming a device on a semiconductor substrate of a first conductivity type, the method comprising: forming a semiconducting layer on...
5455189 Method of forming BICMOS structures  
In a bipolar or BiCMOS process, a heavily doped buried layer of a first conductivity type and a heavily doped channel stop region of a second conductivity type are formed in a lightly doped...
Matches 1 - 50 out of 122 1 2 3 >