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6258692 Method forming shallow trench isolation  
The invention provides a method of forming shallow trench isolation. In the method, a first mask and a second mask layer are made of polysilicon and silicon oxide, respectively. Part of the first...
6255207 Composite planarizing dielectric layer employing high density plasma chemical vapor deposited (HDP-CVD) underlayer  
A method for forming upon a substrate employed within a microelectronics fabrication a composite dielectric layer having etched via contact holes in which via poisoning is attenuated. There is...
6251748 Method of manufacturing shallow trench isolation structure  
A method of manufacturing shallow trench isolation structure comprising the steps of forming a polysilicon mask layer over a substrate, and then patterning the polysilicon mask layer and the...
6245642 Process for planarizing buried oxide films in trenches by applying sequential diverse CMP treatments  
The present invention provides a process for manufacturing a semiconductor structure comprising the steps of: (a) forming a first SiN film on a semiconductor substrate; (b) patterning the first SiN...
6245641 Semiconductor device comprising trench isolation insulator film and method of fabricating the same  
A first trench having a first width and a second trench having a width which is smaller than the first width are formed on a major surface of a semiconductor substrate. A first isolation insulator...
6245638 Trench and gate dielectric formation for semiconductor devices  
Semiconductor device fabrication techniques which integrate the formation of trench isolation areas and gate insulating layers are provided. The fabrication techniques include forming one or more...
6242323 Semiconductor device and process for producing the same  
A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by...
6221736 Fabrication method for a shallow trench isolation structure  
A method for fabricating a shallow trench isolation structure is described, in which a pad oxide layer, a silicon oxy-nitride layer and the silicon nitride layer are sequentially formed on the...
6221735 Method for eliminating stress induced dislocations in CMOS devices  
The stress dislocations formed in a substrate by semiconductor processing are significantly reduced, if not eliminated, by subjecting the substrate to a high temperature post sacrificial oxide...
6218284 Method for forming an inter-metal dielectric layer  
A method for forming an inter-metal dielectric layer without voids therein is described. Wiring lines are formed on a provided substrate. Each of the wiring lines comprises a protective layer...
6218267 Shallow trench isolation method of a semiconductor wafer  
The present invention relates to a shallow trench isolation method of a semiconductor wafer for filling dielectric material in each shallow trench between components on the surface of the...
6214697 Trench isolation for semiconductor devices  
In etching trench isolation structures, a pad oxide or sacrificial oxide may be formed with substantially the same (or higher) etch rate as the trench filler. Because the etch rate in the trench...
6207535 Method of forming shallow trench isolation  
A method of fabricating shallow trench isolations (STI) which forms a substrate with a patterned first oxide layer and a patterned silicon nitride layer thereon, so that active regions are defined...
6207513 Spacer process to eliminate corner transistor device  
A method for forming spacers for preventing formation of parasitic corner devices in transistors includes etching trenches into a semiconductor substrate to form an active area region, lining the...
6204146 Method of fabricating shallow trench isolation  
A method of fabricating a shallow isolation. The method comprises the step of forming a pad oxide layer and a mask layer over a substrate in turn. The mask layer is patterned. The pad oxide layer...
6203863 Method of gap filling  
A method of gap filling by using HDPCVD. On a substrate having a conductive structure, a first oxide layer is formed to protect the conductive structure. While forming the first oxide layer no bias...
6200880 Method for forming shallow trench isolation  
A method for forming a shallow trench isolation used to isolate a device is provided. A pad oxide and a mask layer are formed on a substrate and patterned. A trench is formed within the substrate...
6197661 Semiconductor device with trench isolation structure and fabrication method thereof  
A semiconductor device with the trench isolation structure is provided, in which the leakage current problem does not occur. This device is comprised ofa semiconductor substrate, an isolation...
6197660 Integration of CMP and wet or dry etching for STI  
Shallow trench isolation in which trenches having varying dimensions have been formed in a hard surface such as silicon nitride can lead to dishing inside the larger trenches. To overcome this, the...
6194285 Formation of shallow trench isolation (STI)  
A method is disclosed to form a shallow trench isolation (STI) having reduced junction leakage by avoiding undercutting near the shoulder of the trench. This is accomplished by using the pad oxide...
6191003 Method for planarizing a polycrystalline silicon layer deposited on a trench  
A method for planarizing a polycrystalline silicon layer deposited on a trench, which is formed on a semiconductor substrate, comprises the following steps. First, a polycrystalline silicon layer...
6180515 Method of fabricating self-align contact window with silicon nitride side wall  
A gate oxide layer, a polysilicon layer are patterned on a substrate. Then, a thermal oxidation is carried out to form the first silicon dioxide layer on the surface of the polysilicon layer. Then,...
6180493 Method for forming shallow trench isolation region  
A method for forming shallow trench isolation region. The method includes the steps of forming spacers on the sidewalls of a patterned mask layer and a pad oxide layer, and then etching the...
6180492 Method of forming a liner for shallow trench isolation  
An improved method for forming shallow trench isolation structure is described. The present method comprises the steps of providing a pad oxide layer and a mask layer on a semiconductor substrate...
6180490 Method of filling shallow trenches  
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to an improved method of filling shallow trenches, in shallow trench...
6174808 Intermetal dielectric using HDP-CVD oxide and SACVD O3-TEOS  
Method for forming an inter-level dielectric layer upon a substrate employed within a microelectronics fabrication. There is first provided a substrate. There is then formed upon the substrate a...
6174785 Method of forming trench isolation region for semiconductor device  
Shallow trench isolation regions in a semiconductor device are formed by utilizing sacrificial spacers such as polysilicon spacers having a rounded shape to form trench isolation areas. The spacer...
6165871 Method of making low-leakage architecture for sub-0.18 μm salicided CMOS device  
A method for forming a stepped shallow trench isolation is described. A pad oxide layer is deposited on the surface of a semiconductor substrate. A first nitride layer is deposited overlying the...
6159823 Trench isolation method of semiconductor device  
A trench isolation method is provided that prevents the formation of a dent between a trench isolation region and an active region and prevents the generation of water spots during a cleaning...
6156620 Isolation trench in semiconductor substrate with nitrogen-containing barrier region, and process for forming same  
An isolation trench in a silicon semiconductor substrate is provided with a barrier region containing nitrogen atoms formed in the trench, contiguous with the silicon semiconductor substrate...
6150234 Trench-diffusion corner rounding in a shallow-trench (STI) process  
An isolation structure on an integrated circuit is formed using a shallow trench isolation process. On a substrate, a trench is formed. A thermal anneal is performed to oxidize exposed areas of the...
6150233 Semiconductor device and method of manufacturing the same  
An underlaid silicon oxide film (2) and a polycrystalline silicon film (5) are formed in this order on a surface (1S) of a silicon substrate (1). The polycrystalline silicon film (5) and the...
6146975 Shallow trench isolation  
The specification describes a dual patterned polish stop layer technique for shallow trench isolation. The shallow trenches are formed by etching trenches in a semiconductor substrate wafer,...
6146974 Method of fabricating shallow trench isolation (STI)  
A method of fabricating shallow trench isolation (STI) forms a trench in a substrate and a liner oxide layer in the trench. A first high density plasma chemical vapor deposition (HDPCVD) is...
6143672 Method of reducing metal voidings in 0.25 μm AL interconnect  
In one embodiment, the present invention relates to a method of depositing a dielectric layer over a stacked interconnect structure, involving the steps of: providing a substrate having at least...
6140208 Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications  
A reduction in parasitic leakages of shallow trench isolation vias is disclosed wherein the distance between the silicon nitride liner and the active silicon sidewalls is increased by depositing an...
6136664 Filling of high aspect ratio trench isolation  
A method of forming a trench isolation on a semiconductor substrate comprising the steps of forming a trench in the substrate, partially filling the trench with a first layer of polysilicon,...
6133105 Method of manufacturing borderless contact hole including a silicide layer on source/drain and sidewall of trench isolation structure  
A method of manufacturing a borderless contact hole. A substrate having a pad oxide layer and a silicon nitride layer formed thereon is provided. A trench is formed to penetrate through the silicon...
6130126 Self-planarizing DRAM chip avoids edge flaking  
The dummy oxide used to form DRAM capacitor cells is left in place over the peripheral transistors, reducing the height difference between the DRAM array and the peripheral circuitry and protecting...
6127241 Trench isolation structure and fabrication method thereof  
Trench isolation structure includes a first conformal insulating film (preferably consisting of silicon nitride) which lines a trench etched in a silicon substrate, an insulating layer (preferably...
6118168 Trench isolation process using nitrogen preconditioning to reduce crystal defects  
A method of forming a trench isolation structure in a semiconductor substrate. After etching a trench into the semiconductor substrate, an oxide layer is formed within the trench. The surface of...
6117743 Method of manufacturing MOS device using anti reflective coating  
A method of manufacturing MOS device including the steps of providing a semiconductor substrate that has a device isolation structure thereon, and then depositing a gate oxide layer, a polysilicon...
6114220 Method of fabricating a shallow trench isolation  
A method of fabricating a shallow trench isolation includes formation of a trench in a substrate. An oxide layer is formed on the substrate to fill the trench. A barrier layer and a coating layer...
6114217 Method for forming isolation trenches on a semiconductor substrate  
Disclosed is a method for providing an insulation trench on a semiconductor substrate. The method includes the steps of depositing a pad oxide layer and a nitride layer on a semiconductor...
6110801 Method of fabricating trench isolation for IC manufacture  
A method of fabricating trench isolation is disclosed: firstly, the areas of trench isolation are formed on a silicon substrate, and then filled by depositing an oxide layer. Secondly, a process of...
6107143 Method for forming a trench isolation structure in an integrated circuit  
A method is provided for forming a trench isolation structure in an integrated circuit that has a better reliability and an acceptable time-dependent dielectric breakdown over a greater range of...
6103595 Assisted local oxidation of silicon  
A method for forming a semiconductor device comprises the steps of providing a semiconductor substrate having first and second surfaces, the second surface having an inferior plane with respect to...
6100163 Gap filling of shallow trench isolation by ozone-tetraethoxysilane  
A method for filling a trench within a silicon substrate. There is first provided a silicon substrate having a trench formed therein. There is then oxidized thermally the silicon substrate to form...
6100161 Method of fabrication of a raised source/drain transistor  
A method of fabricating a transistor, comprising the following steps. A silicon semiconductor substrate having a pad oxide portion within an active area is provided. A polysilicon layer is...
6096623 Method for forming shallow trench isolation structure  
A method for forming a shallow trench isolation structure. A pad oxide layer is formed over a substrate. A hard mask layer is formed over the pad oxide layer. A portion of the hard mask layer, the...
Matches 151 - 200 out of 357 < 1 2 3 4 5 6 7 8 >