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5994201 Method for manufacturing shallow trench isolation regions  
A method for manufacturing shallow trench isolation regions according to the invention uses a first stop layer and a second stop layer as two polishing stop layers, or a polishing stop layer and an...
5994200 Trench isolation structure of a semiconductor device and a method for thereof  
A semiconductor device isolation structure includes a trench formed in a substrate vertically from the major surface of the substrate, a trench plug for filling the trench, and a buried insulation...
5989978 Shallow trench isolation of MOSFETS with reduced corner parasitic currents  
A method is described for forming MOSFETs with shallow trench isolation wherein the abrupt corners introduced by anisotropically etching the silicon trenches are modified by an oxidation step which...
5989975 Method for manufacturing shallow trench isolation  
A method for manufacturing shallow trench isolation comprising the steps of providing a substrate, then forming a pad oxide layer over a substrate using a thermal oxidation process. After that, a...
5985735 Trench isolation process using nitrogen preconditioning to reduce crystal defects  
A method of forming a trench isolation structure in a semiconductor substrate. After etching a trench into the semiconductor substrate, an oxide layer is formed within the trench. The surface of...
5981357 Semiconductor trench isolation with improved planarization methodology  
An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having...
5981356 Isolation trenches with protected corners  
A method for forming trench isolation with spacers on the corners where the silicon and oxide intercept. A cavity is formed in silicon with a mask. Prior to completely removing the mask, the mask...
5976951 Method for preventing oxide recess formation in a shallow trench isolation  
A method for forming an isolating trench in a substrate is disclosed herein. The forgoing method includes the following steps. First, form a first dielectric layer and a second dielectric layer on...
5976949 Method for forming shallow trench isolation  
A method for forming shallow trench isolation that can avoid dishing effect produced by a conventional manufacturing process. The method utilizes photolithographic and etching techniques to define...
5976948 Process for forming an isolation region with trench cap  
A method for producing a semiconductor device using an improved trench isolation technique includes, first, forming a masking layer over a device layer. A first portion of the masking layer and an...
5972774 Process for fabricating a semiconductor device having contact hole open to impurity region coplanar with buried isolating region  
A MIS type field effect transistor has a source/drain region overlain by a titanium silicide layer contiguous to an upper silicon nitride layer of a buried isolating structure embedded into a...
5970363 Shallow trench isolation formation with improved trench edge oxide  
A shallow trench isolation structure is formed which enables the growth of a high quality gate oxide at the trench edges. Embodiments include forming a photoresist mask directly on a pad oxide...
5968610 Multi-step high density plasma chemical vapor deposition process  
A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the deposition of three oxide layers using high density plasma...
5960300 Method of manufacturing semiconductor device  
On a semiconductor substrate are successively deposited a silicon dioxide film and a silicon nitride film. The silicon nitride film, the silicon dioxide film, and the semiconductor substrate are...
5960299 Method of fabricating a shallow-trench isolation structure in integrated circuit  
A semiconductor fabrication method is provided for fabricating a shallow-trench isolation (STI) structure in an integrated circuit, which can prevent the occurrence of microscratches in the oxide...
5943590 Method for improving the planarity of shallow trench isolation  
A method for improving the planarity of a semiconductor chip using chemical-mechanical polishing during a shallow trench isolation process is described. Specifically, an polish-stop layer,...
5940717 Recessed shallow trench isolation structure nitride liner and method for making same  
A method for reducing hot carrier reliability problems within an integrated circuit device. The method includes forming a shallow trench isolation structure incorporated with the device by filling...
5933749 Method for removing a top corner of a trench  
A method for removing the top corner of the trench is disclosed. After the formation of an oxide layer and then a nitride layer over a substrate, a portion of the nitride layer, the oxide layer and...
5933747 Method and structure for an advanced isolation spacer shell  
A method and structure are provided for a spacer shell structure which is formed of dielectric materials seletive to one another. The dielectric materials can be configured into a chosen geometric...
5926723 Generation of a loose planarization mask having relaxed boundary conditions for use in shallow trench isolation processes  
A method of forming an improved planarization mask for shallow trench isolation process area in integrated circuit manufacturing is disclosed. The planarization mask is generated automatically by...
5926713 Method for achieving global planarization by forming minimum mesas in large field areas  
An isolation technique is provided for improving the overall planarity of trench isolation regions relative to adjacent silicon mesas. The isolation process results in a spaced plurality of silicon...
5923993 Method for fabricating dishing free shallow isolation trenches  
A fabrication process for manufacturing integrated circuits with isolation trenches. The process includes the use of two nitride layers and an oxide layer formed by high density plasma oxidation,...
5918131 Method of manufacturing a shallow trench isolation structure  
A method of manufacturing a shallow trench isolation structure that utilizes the early formation of a strong oxide spacers so that for any subsequent pad oxide layer or sacrificial oxide layer...
5915192 Method for forming shallow trench isolation  
A method of forming a trench isolation is disclosed. The initial step includes forming a first dielectric layer on a substrate of a transistor followed by a second dielectric layer formed on the...
5910018 Trench edge rounding method and structure for trench isolation  
The present invention provides a method to achieve shallow trench isolation (STI) on the quarter-micron scale. A thin oxide layer, a thick nitride layer, a thick oxide layer and a thin nitride...
5904541 Method for fabricating a semiconductor device having a shallow trench isolation structure  
A semiconductor device having a shallow trench isolation structure, where the upper part of the trench is broader than the lower part of it, comprises an insulating layer on the sidewalls of the...
5904539 Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties  
An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having...
5904538 Method for developing shallow trench isolation in a semiconductor memory device  
A method for developing shallow trench isolation in a semiconductor device includes forming an ion diffusion area by implanting fluorine ions where a trench is to be formed in a semiconductor...
5902127 Methods for forming isolation trenches including doped silicon oxide  
A method for forming a microelectronic structure includes the steps of forming a trench in a substrate and forming an insulating layer which fills the trench and covers the substrate. Ions can be...
5897361 Semiconductor device and method of producing same  
A trench 13 is formed to isolate a first region 11a and a second region 11b where elements of a semiconductor substrate 11 such as a silicon substrate are formed, and a lamination layer of a first...
5895254 Method of manufacturing shallow trench isolation structure  
A method for forming a shallow trench isolation structure comprising the steps of sequentially forming a pad oxide layer and a mask layer over a substrate, then patterning the mask layer and the...
5885883 Methods of forming trench-based isolation regions with reduced susceptibility to edge defects  
Methods of forming trench-based isolation regions with reduced susceptibility to edge defects include the steps of forming trenches at a face of a semiconductor substrate and then filling the...
5874345 Method for planarizing TEOS SiO.sub.2 filled shallow isolation trenches  
According to the present invention, there is disclosed a method for planarizing TEOS SiO 2 filled shallow isolation trenches according to a planarization main step which is comprised of three...
5872045 Method for making an improved global planarization surface by using a gradient-doped polysilicon trench--fill in shallow trench isolation  
A method for fabricating shallow trench isolation using a gradient-doped polysilicon trench-fill and a chemical/mechanical polishing that improves substrate planarity was achieved. The method...
5863827 Oxide deglaze before sidewall oxidation of mesa or trench  
A shallow trench isolation (STJ) (10) is used to isolate two active regions (12) from each other. The advantage of STI (10) is that the upper corners (14) are rounded. Rounding of the upper corners...
5854114 Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide  
A shallow trench isolation structure and a method for forming the same for use with non-volatile memory devices is provided so as to maintain sufficient data retention thereof. An epitaxial layer...
5837612 Silicon chemical mechanical polish etch (CMP) stop for reduced trench fill erosion and method for formation  
A method for forming shallow trench isolation (STI) (100) begins by forming an oxidizable layer (106) preferably made of polysilicon. An opening is patterned and etched through this layer (106) to...
5834358 Isolation regions and methods of forming isolation regions  
A silicon-comprising layer is employed adjacent a trench during planarization of an oxide fill within the trench. An overhanging oxide sidewall is formed along a lateral edge of a trenched...
5817567 Shallow trench isolation method  
An improved method for implementing shallow trench isolation in integrated circuits is described. The method begins with the formation of trenches, through patterning and etching. These trenches...
5811347 Nitrogenated trench liner for improved shallow trench isolation  
A method of forming an improved isolation trench between active regions within the semiconductor substrate. The improved method incorporates a trench liner having a nitrogen content of...
5804490 Method of filling shallow trenches  
A method of isolation in silicon integrated circuit processing overfills the trench by a fill margin, deposits a temporary layer of poly having a thickness less than the trench depth by the...
5801083 Use of polymer spacers for the fabrication of shallow trench isolation regions with rounded top corners  
A method for forming insulator filled, shallow trench isolation regions, with rounded corners, has been developed. The process features the use of a polymer coated opening, in an insulator layer,...
5795811 Method for forming insulating films in semiconductor devices  
A method of forming an isolating trench device in a semiconductor device comprising the steps of; sequentially forming a first material layer and a second material layer over a surface of a...
5786262 Self-planarized gapfilling for shallow trench isolation  
A new method is disclosed to form a shallow trench isolation with a ozone-TEOS as a gapfilling material. The formation of the shallow trench isolation described herein includes a pad layer, a...
5780325 Methods of making isolations including doped edge layer, for semiconductor-on-insulator substrates  
Isolation regions for a semiconductor layer of a semiconductor-on-insulator substrate are fabricated by forming a patterned implantation mask on the semiconductor layer. The patterned implantation...
5763315 Shallow trench isolation with oxide-nitride/oxynitride liner  
Disclosed is an improved process and liner for trench isolation which includes either a single oxynitride layer or a dual oxynitride (or oxide)/nitride layer. Such a process and liner has an...
5753562 Methods of forming semiconductor devices in substrates having inverted-trench isolation regions therein  
Methods of forming semiconductor substrates having inverted-trench isolation regions therein include the steps of forming at least one trench in a semiconductor substrate at a first face thereof...
5742091 Semiconductor device having a passive device formed over one or more deep trenches  
A semiconductor device includes at least one passive device and is configured such that parasitic capacitances associated with the passive device are minimized. A substrate layer of the...
5741740 Shallow trench isolation (STI) method employing gap filling silicon oxide dielectric layer  
A method for filling a trench within a silicon substrate. There is first provided a silicon substrate having a trench formed therein. There is then oxidized thermally the silicon substrate to form...
5731241 Self-aligned sacrificial oxide for shallow trench isolation  
The present invention provides a method of manufacturing a sacrificial self aligned sub-atmospheric chemical vapor deposition (SACVD) O 3 TEOS layer 50 70 over a trench oxide 40 to protect the...
Matches 451 - 500 out of 530 < 1 2 3 4 5 6 7 8 9 10 11 >