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7622769 |
Isolation trench
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the...
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7566612 |
Method of fabricating capacitor in semiconductor device and semiconductor device using the same
A method of fabricating a capacitor in a semiconductor device is provided. The method includes steps of depositing a metal layer for forming a lower electrode on a semiconductor substrate; forming,...
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7541259 |
Semiconductor device having a compressed device isolation structure
The semiconductor device includes a lower device isolation structure formed in a semiconductor substrate to define an active region. The lower device isolation structure has a first compressive...
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7479440 |
Method of forming an isolation structure that includes forming a silicon layer at a base of the recess
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited...
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7470595 |
Oxidizing a metal layer for a dielectric having a platinum electrode
A tight contact layer is disposed on a semiconductor substrate, the tight contact layer being made of one material selected from the group consisting of refractory metal, alloy of refractory metal,...
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7422961 |
Method of forming isolation regions for integrated circuits
A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The...
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7402886 |
Memory with self-aligned trenches for narrow gap isolation regions
Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region...
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7371655 |
Method of fabricating low-power CMOS device
A low-power CMOS device can be fabricated by forming a shallow trench on a silicon substrate using a gate mask and negative photoresist. This enables an extremely low profile for a junction after...
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7365362 |
Semiconductor device and method of fabricating semiconductor device using oxidation
According to one aspect of the invention, there is provided a semiconductor device fabrication method comprising:
forming a gate insulating film on a semiconductor substrate; forming a film...
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7361558 |
Method of manufacturing a closed cell trench MOSFET
Embodiments of the present invention provide an improved closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The closed cell TMOSFET comprises a drain, a body region...
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7303961 |
Method for producing a junction region between a trench and a semiconductor zone surrounding the trench
A method for producing a junction region ( 2, 5, 6, 7 ) between a trench ( 3 ) and a semiconductor zone ( 2 ) surrounding the trench ( 3 ) in a trench semiconductor device ( 1 ) has the following...
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7300855 |
Reversible oxidation protection of microcomponents
In a method for the reversible oxidation protection of microcomponents, a substrate is provided, a silicon nitride layer is provided on the substrate in order to protect it against oxidation, an...
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7300884 |
Pattern forming method, underlayer film forming composition, and method of manufacturing semiconductor device
According to an aspect of the invention, there is provided a pattern forming method comprising forming an underlayer film on a film to be worked which has been formed on a semiconductor substrate,...
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7288463 |
Pulsed deposition layer gap fill with expansion material
Conformal dielectric deposition processes supplemented with a deposited expansion material can fill high aspect ratio narrow width gaps with significantly reduced incidence of voids or weak spots....
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7279394 |
Method for forming wall oxide layer and isolation layer in flash memory device
Disclosed herein are methods for forming wall oxide films in flash memory devices and methods for forming isolation films. After trenches are formed in the substrate, an ISSG (In-Situ Steam...
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7262110 |
Trench isolation structure and method of formation
In general, the present invention discloses at least one trench isolation region formed in a semiconductor substrate to electrically and/or optically isolate at least one active region from another...
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7259074 |
Trench isolation method in flash memory device
The present invention provides a trench isolation method in a flash memory device, by which stability and reliability of the device are enhanced in a manner of forming a pad oxide layer thick in...
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7253065 |
Self-aligned nanotube field effect transistor and method of fabricating same
A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the...
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7238588 |
Silicon buffered shallow trench isolation
A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The...
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7214595 |
Method of producing semiconductor devices
A method of producing semiconductor devices is provided, which makes it possible to bury a silicon oxide without shape deterioration in device isolation trenches. The method comprises the steps of:...
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7160782 |
Method of manufacture for a trench isolation structure having an implanted buffer layer
The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure...
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7148158 |
Semiconductor device and method for manufacturing the same
A semiconductor device includes a semiconductor device comprising a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulation film formed on the...
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7132729 |
Semiconductor device and method of manufacturing same
The present invention provides a semiconductor device formed with a diode array together with bipolar transistors, which is capable of preventing the occurrence of crystal defects developed in...
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7112513 |
Sub-micron space liner and densification process
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the...
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7071073 |
Process for manufacturing low-cost and high-quality SOI substrates
For manufacturing an SOI substrate, the following steps are carried out: providing a wafer of semiconductor material; forming, inside the wafer, a plurality of passages forming a labyrinthine...
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7067387 |
Method of manufacturing dielectric isolated silicon structure
A method for fabricating dielectric isolated silicon islands or regions is described in this invention. A hard composite mask of pad oxide and silicon nitride is first patterned on a silicon...
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7053007 |
Method for fabricating semiconductor integrated circuit device
A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and...
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7041547 |
Methods of forming polished material and methods of forming isolation regions
In one aspect, the invention encompasses a method of forming a polished material. A substrate is provided and an elevational step is provided relative to the substrate. The elevational step has an...
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7029988 |
Fabrication method and device structure of shallow trench insulation for silicon wafer containing silicon-germanium
A method and device are provided for shallow trench isolation for a silicon wafer containing silicon-germanium. In one example, the method comprises forming a trench region in a silicon-germanium...
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7015115 |
Method for forming deep trench isolation and related structure
According to one embodiment, a structure comprises a substrate and a field oxide region, where the field oxide region has a top surface, and where the top surface of the field oxide region...
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7012010 |
Methods of forming trench isolation regions
In accordance with an aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A silanol layer is formed to partially fill the trench and...
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6962856 |
Method for forming device isolation film of semiconductor device
A method for forming a device isolation film of a semiconductor device, wherein an annealing process is performed on the oxide film using NH3 prior to the deposition of a liner nitride film and...
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6955973 |
Method for forming a semiconductor device
A metal film containing a metal is formed on a silicon layer, and then a surface portion of the silicon layer and the metal film are oxidized so as to form a silicon oxide film containing the metal...
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6930018 |
Shallow trench isolation structure and method
Disclosed is a shallow trench isolation (STI) structure and methods of manufacturing the same. The methods eliminate the requirement for design size adjustments (DSA) in manufacturing the STI...
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6927138 |
Method of semiconductor device fabrication
Provided is a method of semiconductor device fabrication capable of rounding the sharp edge portions of trenches so as to form device isolation regions having high electrical reliability. A...
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6911405 |
Semiconductor device and method of manufacturing the same
A process gas consisting of one of N 2 , N 2 O or a mixture thereof is converted to a plasma and then a surface of a copper wiring layer is exposed to the plasma of the process gas, whereby a...
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6884687 |
SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY, FORMING CONDUCTIVE LINES, FORMING A CONDUCTIVE GRID, FORMING A CONDUCTIVE NETWORK, FORMING AN ELECTRICAL INTERCONNECTION TO A NODE LOCATION, FORMING AN ELECTRICAL INTERCONNECTION WITH A TRANSISTOR SOURCE/DRAIN REGION, AND INTEGRATED CIRCUITRY
In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in...
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6875669 |
Method of controlling the top width of a deep trench
A method of controlling the top width of a deep trench. A conductive layer is formed on the trench over a substrate of polysilicon with a recessed structure. An additional layer of amorphous...
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6855633 |
Method for fabricating semiconductor device
A mask ( 4 ) for forming active regions is formed on a surface portion of a Si layer ( 2 ) serving as a semiconductor region with a thermal oxide film ( 3 ) interposed therebetween. Dummy sidewalls...
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6849520 |
Method and device for forming an STI type isolation in a semiconductor device
A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide...
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6833330 |
Method to eliminate inverse narrow width effect in small geometry MOS transistors
A method of making a semiconductor structure includes sealing a gate layer by wet oxidation. The gate layer is on a substrate containing isolation regions. Semiconductor devices prepared from the...
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6812115 |
Method of filling an opening in a material layer with an insulating material
The filling of sub-0.25 μm trenches with dielectric material may lead to the formation of a void. Typically, the void may be closed by oxidation. When the trench includes non-oxidizable sidewall...
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6806501 |
Integrated circuit having SiC layer
The present invention is related to an integrated circuit having an SiC etch stop layer fabricated using a method for removal of silicon carbide layers and in particular amorphous SiC of a...
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6794279 |
Passivating inorganic bottom anti-reflective coating (BARC) using rapid thermal anneal (RTA) with oxidizing gas
A method is provided, the method including forming a gate dielectric layer above a substrate layer and forming a gate conductor layer above the gate dielectric layer. The method also includes...
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6787409 |
Method of forming trench isolation without grooving
A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines...
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6784055 |
Flash memory device and a method for fabricating the same
A flash memory having a charge-storage dielectric layer and a method for forming the same are provided. According to one embodiment, charge-storage dielectric layers are formed over the first and...
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6756274 |
Fabrication process for a super-self-aligned trench-gated DMOS with reduced on-resistance
A super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single...
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6737336 |
Semiconductor device and manufacturing method therefor
A semiconductor device having a trench isolation structure which has a high insulating characteristic, is suitable for miniaturizing a semiconductor device, and prevents a leakage current, as well...
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6727157 |
Method for forming a shallow trench isolation using air gap
In fabricating a shallow trench isolation (STI), a silicon oxide layer, a silicon nitride layer and a moat pattern is sequentially deposited on a silicon substrate. Next, the silicon nitride layer...
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6724027 |
Magnetic shielding for MRAM devices
A magnetic random access memory module includes a magnetic memory array. A permeable metal layer extends over a first side of the magnetic memory array. An electrically insulating layer is disposed...
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