Patents in Class 438/427

Matches 1 - 50 out of 420

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Match	Document	Document Title
1	7622787	Process for high voltage superjunction termination A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each...
2	7622369	Device isolation technology on semiconductor substrate A method of forming device isolation regions on a trench-formed silicon substrate and removing residual carbon therefrom includes providing a flowable, insulative material constituted by silicon,...
3	7622360	Shallow trench isolation region in semiconductor device and method of manufacture A method of forming a device isolation region in a semiconductor device is capable of completely removing an oxide layer for trench formation in a central region of the semiconductor device without...
4	7612427	Apparatus for confining inductively coupled surface currents A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep...
5	7611963	Method for forming a multi-layer shallow trench isolation structure in a semiconductor device A method for forming a multi-layer shallow trench isolation structure in a semiconductor device is described. In one embodiment, the method includes etching a shallow trench in a silicon substrate...
6	7611962	Method for fabricating semiconductor device A method for fabricating a semiconductor device can prevent a leakage current and the decrease of threshold voltage by rounding corners of a trench. The method may include the steps of forming a...
7	7601609	Method for manufacturing device isolation film of semiconductor device A method for manufacturing device isolation film of semiconductor device is disclosed. The method utilizes a plasma oxidation of a liner nitride film exposed by etching a liner oxide the film in...
8	7601608	Memory array buried digit line A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is...
9	7601607	Protruded contact and insertion of inter-layer-dielectric material to match damascene hardmask to improve undercut for low-k interconnects An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in...
10	7595254	Method of manufacturing a semiconductor device Embodiments relate to a method for manufacturing a semiconductor device, which may reduce damage due to stress of an STI bottom corner during an ion implantation and annealing being subsequent...
11	7595252	Method of manufacturing a semiconductor memory device A method of manufacturing a semiconductor device comprises providing a semiconductor substrate, forming trenches in predetermined regions of the semiconductor substrate, forming isolation...
12	7579255	Semiconductor device and method for isolating the same The present invention relates to a semiconductor device and a method for isolating the same. The semiconductor device includes: a silicon substrate provided with a trench including at least one...
13	7575992	Method of forming micro patterns in semiconductor devices A method of forming a micro pattern in a semiconductor device is disclosed. An oxide film mask is divided into a cell oxide film mask and a peri oxide film mask. Therefore, a connection between the...
14	7575981	Method for fabricating isolation layer in semiconductor device A method for fabricating an isolation layer in a semiconductor device includes providing a substrate, forming a trench over the substrate, forming a liner nitride layer and a liner oxide layer...
15	7572713	Method of fabricating semiconductor device with STI structure A semiconductor device such as a flash memory includes a semiconductor substrate having a surface, and a plurality of trenches formed in the substrate so as to be open at the surface of the...
16	7560359	Methods of forming asymmetric recesses and gate structures that fill such recesses and related methods of forming semiconductor devices that include such recesses and gate structures In a method of forming an asymmetric recess, an asymmetric recessed gate structure filling the asymmetric recess, a method of forming the asymmetric recessed gate structure, a semiconductor device...
17	7560357	Method for creating narrow trenches in dielectric materials A method for producing narrow trenches in semiconductor devices. The narrow trenches are formed by chemically changing the properties of a first dielectric layer locally, such that the side walls...
18	7557031	Etch back with aluminum CMP for LCOS devices A method for manufacturing an LCOS device includes forming an interlayer dielectric layer overlying a surface region of a substrate. The interlayer dielectric layer is patterned to form a plurality...
19	7553767	Method for fabricating semiconductor device having taper type trench A method for fabricating a semiconductor includes: etching a substrate to a predetermined depth to form an upper trench with taper edges; etching the substrate beneath the upper trench to form a...
20	7553741	Manufacturing method of semiconductor device Even if the insulated isolation structure which makes element isolation using partial and full isolation combined use technology is manufactured, the manufacturing method of a semiconductor device...
21	7550363	Method of fabricating a semiconductor device having first and second trenches using non-concurrently formed hard mask patterns A semiconductor device comprising a trench device isolation layer and a method for fabricating the semiconductor device are disclosed. The method comprises forming a plurality of first trenches on...
22	7547610	Method of making a semiconductor device comprising isolation trenches inducing different types of strain By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted...
23	7544592	Method for increasing etch rate during deep silicon dry etch A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is...
24	7544582	Semiconductor device and method for fabricating the same A semiconductor device and a method for fabricating the same may improve the isolation characteristics without deterioration of the junction diode characteristics and an increase in a threshold...
25	7534723	Methods of forming fine patterns, and methods of forming trench isolation layers using the same Methods of forming a fine pattern include forming an underlying layer on a substrate, forming preliminary hard mask patterns having a first pitch on the underlying layer, the preliminary hard mask...
26	7531415	Multilayered CMP stop for flat planarization A three layer film ( 116/114/112 ), such as nitride/oxide/nitride for a CMP stop layer ( 110 ). A gap filling material ( 120 ) is polished, stopping on the first film ( 112 ). The first film ( 112...
27	7531409	Fabrication method and structure for providing a recessed channel in a nonvolatile memory device A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array...
28	7524732	Semiconductor device with L-shaped spacer and method of manufacturing the same A semiconductor device with an L-shape spacer and the method for manufacturing the same are provided. The semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating...
29	7521333	Methods of fabricating trench isolation structures having varying depth A device isolation structure of semiconductor device includes a semiconductor substrate having a cell region, a low voltage region and a high voltage region defined therein. A cell trench isolation...
30	7514337	Semiconductor device using EPI-layer and method of forming the same A method of fabricating a semiconductor device includes forming a pad oxide film and a nitride film on a semiconductor substrate; exposing the semiconductor substrate by selectively etching the pad...
31	7498226	Method for fabricating semiconductor device with step gated asymmetric recess A method for fabricating a semiconductor device with a step gated asymmetric recess is provided. The method includes: forming an organic bottom anti-reflective coating (BARC) layer over a...
32	7485544	Strained semiconductor, devices and systems and methods of formation In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The device region has a channel region, and...
33	7470597	Method of fabricating a multilayered dielectric diffusion barrier layer A method of fabricating a structure including a low-k multilayered dielectric diffusion barrier layer having at least one low-k sublayer and at least one air barrier sublayer is described herein....
34	7465643	Semiconductor device with fixed channel ions A method for manufacturing a semiconductor device includes subjecting a semiconductor substrate to thermal treatment at a temperature ranging from 770 to 830° C. to fix channel ions then forming a...
35	7439604	Method of forming dual gate dielectric layer A semiconductor device includes a dual gate dielectric layer that increases a performance of a semiconductor device. The semiconductor device includes a first dielectric layer having a...
36	7427553	Fabricating method of semiconductor device A fabricating method of a semiconductor device is provided. The method comprises the steps of preparing a semiconductor substrate having an active area with a high voltage device area and a low...
37	7420259	Semiconductor device having two-layered charge storage electrode A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate...
38	7419878	Planarized and silicided trench contact Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends...
39	7416956	Self-aligned trench filling for narrow gap isolation regions Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region...
40	7396738	Method of forming isolation structure of flash memory device A method of forming a semiconductor memory device includes providing a semiconductor substrate having a cell region and a peripheral region. A gate dielectric layer is formed over the semiconductor...
41	7396728	Methods of improving drive currents by employing strain inducing STI liners A method forms a semiconductor device comprising isolation structures that selectively induce strain into active regions of NMOS and PMOS devices. Form a hard mask layer over a semiconductor body....
42	7393789	Protective coating for planarization Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed,...
43	7387940	Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated...
44	7371655	Method of fabricating low-power CMOS device A low-power CMOS device can be fabricated by forming a shallow trench on a silicon substrate using a gate mask and negative photoresist. This enables an extremely low profile for a junction after...
45	7371645	Method of manufacturing a field effect transistor device with recessed channel and corner gate device Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench...
46	7368365	Memory array buried digit line A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is...
47	7364980	Manufacturing method of semiconductor substrate Closure at the opening of a trench with an epitaxial film is restrained, and thereby, filling morphology in the trenches is improved. A method for manufacturing a semiconductor substrate includes a...
48	7354828	Semiconductor device with increased channel length and method for fabricating the same A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the...
49	7354786	Sensor element with trenched cavity A micromechanical sensor element and a method for the production of a micromechanical sensor element that is suitable, for example in a micromechanical component, for detecting a physical quantity....
50	7332419	Structure and method of fabricating a transistor having a trench gate An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The...

Matches 1 - 50 out of 420

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