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7638385 Method of forming a semiconductor device and structure therefor  
A method of forming a semiconductor device includes forming isolation trenches that are used to isolate some of the electrical elements such as transistors, diodes, capacitors, or resistors on a...
7473595 Method for decreasing PN junction leakage current of dynamic random access memory  
A method for decreasing a PN junction leakage current of a dynamic random access memory (DRAM), including the steps of: preparing an NMOS transistor formed on a P-type silicon substrate and...
7262110 Trench isolation structure and method of formation  
In general, the present invention discloses at least one trench isolation region formed in a semiconductor substrate to electrically and/or optically isolate at least one active region from another...
7247544 High Q inductor integration  
In an inductor integration process, a high Q inductor is achieved by forming an AlCu inductor via prior to depositing the inductor dielectric.
7169697 Semiconductor device and manufacturing method of the same  
Disclosed is a semiconductor device, comprising a first wiring structure formed on a semiconductor substrate and including a first plug and a first wiring formed on the first plug, and a second...
7163869 Shallow trench isolation structure with converted liner layer  
A STI (shallow trench isolation) structure is formed with a liner layer that is converted from an initial material to a subsequent material. For example, the liner layer is initially comprised of...
7105387 Semiconductor device and manufacturing method for the same  
A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region ( 4 ) and an n-type drift region ( 3 ) are aligned side by side is...
6982193 Method of forming a super-junction semiconductor device  
In one embodiment, a transistor is formed to have alternating depletion and conduction regions that are formed by doping the depletion and conduction regions through an opening in a substrate of...
6977204 Method for forming contact plug having double doping distribution in semiconductor device  
The present invention provides a method for forming a contact plug in a semiconductor device capable of preventing an increase of contact resistance caused by a decrease in dopant concentration and...
6946339 Method for creating a stepped structure on a substrate  
In a method for creating a stepped structure on a substrate, which at least includes a first portion with a first thickness and a second portion with a second thickness, at first a layer sequence...
6927145 Bitline hard mask spacer flow for memory cell scaling  
The invention is a semiconductor device and a method of forming the semiconductor device. The semiconductor device comprises a substrate; buried bitlines formed in the substrate narrower than...
6821824 Semiconductor device and method of manufacturing the same  
A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region ( 4 ) and an n-type drift region ( 3 ) are aligned side by side is...
6699771 Process for optimizing junctions formed by solid phase epitaxy  
A method of forming a semiconductor device includes forming at least one amorphous region within an at least partially formed semiconductor device. The method also includes implanting a halogen...
6696350 Method of fabricating memory device  
A method of fabricating a memory device. A plurality of isolation structures and a plurality of stacked gate structures are sequentially formed on a substrate. While defining the stacked gate...
6537893 Substrate isolated transistor  
A device and a method are provided for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well...
6440805 Method of forming a semiconductor device with isolation and well regions  
A semiconductor device and its method of fabrication are disclosed. The method includes forming a first well region in a semiconductor substrate. The semiconductor substrate includes a first doped...
6406974 Method of forming triple N well utilizing phosphorus and boron ion implantations  
A method of forming a triple N well is described. A first pattern mask layer is formed on a substrate. A first ion implantation step is performed to form an annular longitudinal deep N well in the...
6362035 Channel stop ion implantation method for CMOS integrated circuits  
A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field...
6303463 Method for fabricating a flat-cell semiconductor memory device  
A resist pattern with openings provided at the regions where N + diffusion layers will be eventually formed is formed on a silicon substrate and thereafter, an N-type impurity is ion-doped to form...
6255190 Method for dielectrically isolated deep pn-junctions in silicon substrates using deep trench sidewall predeposition technology  
A method for forming very deep pn-junctions without using epitaxy or extensively high temperature processing is provided. At least two parallel deep trenches are etched into a silicon substrate....
6063687 Formation of trench isolation for active areas and first level conductors  
A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the...
6057184 Semiconductor device fabrication method using connecting implants  
A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device...
6033946 Method for fabricating an isolated NMOS transistor on a digital BiCMOS process  
A method for making an isolated NMOS transistor (10) in a BiCMOS process includes forming an N- conductivity type DUF layer (19) in a P conductivity type semiconductor substrate (12), followed by...
6010926 Method for forming multiple or modulated wells of semiconductor device  
The present invention provide a method for forming a triple well. The triple well includes an n-well, a first p-well surrounded with the n-well and a second p-well apart from the first p-well and...
5985710 Twin well forming method for semiconductor device  
A twin well forming method for a semiconductor device includes the steps of forming a first insulation layer on a semiconductor substrate, selectively etching the first insulation layer to obtain a...
5976921 Method for manufacturing electrostatic discharge protection (ESD) and BiCMOS  
A semiconductor device having an electrostatic discharge protection device and at least one accompanying device selected from the group comprising of a N or P channel MOS transistor, CMOS, bipolar...
5963798 Fabrication method of CMOS device having buried implanted layers for lateral isolation (BILLI)  
A method for fabricating a CMOS device having BILLI (buried implanted layers for lateral isolation) structure capable of effectively preventing latch-up is disclosed, having the following steps. A...
5926704 Efficient method for fabricating P-wells and N-wells  
A method forms, in a CMOS semiconductor substrate, P- and N-wells having independently optimized field regions and active regions. In one embodiment, P- and N-wells are formed by (i) creating in...
5895251 Method for forming a triple-well in a semiconductor device  
A method of forming a triple-well in a semiconductor device, includes the steps of forming a second conductivity type impurity region in a first conductivity type semiconductor substrate, forming...
5891780 Method of fabricating mask ROM using junction isolation  
A semiconductor device comprises a semiconductor substrate formed with at least one well containing impurity ions of either a first conductivity type or a second conductivity type; a plurality of...
5780344 Method for fabricating mask ROM semiconductor device with junction isolation  
A method for fabricating a semiconductor device is provided, which includes the steps of: (i-a) forming at least one impurity region of a first conductivity type in a semiconductor substrate;...
5766970 Method of manufacturing a twin well semiconductor device with improved planarity  
A method for manufacturing semiconductor devices having a twin well structure in which the N-well and P-well regions of the substrate receive differential processing to set the final planarity of...
5705422 Method for forming well of semiconductor device  
A method for forming a well of a semiconductor device sequentially forms a buffer film, an oxidizable film, and an oxidation-blocking film on a periphery area of a semiconductor substrate. A...
5661067 Method for forming twin well  
An improved twin well formation method for a semiconductor device capable of improving the latch-up characteristic in DRAM device which requires a high integration density and of improving a recess...
5624857 Process for fabricating double well regions in semiconductor devices  
A process for fabricating double well regions for a semiconductor device having a first well region of a first type and a second well region of a second type on the substrate is disclosed. The...
5556796 Self-alignment technique for forming junction isolation and wells  
A method in accordance with one embodiment of the present invention may be used to self-align isolation regions, sinkers, and wells. In this improved method, P+ isolation regions, N+ sinkers, and...
5547880 Method for forming a zener diode region and an isolation region  
A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS...
5536665 Method of manufacturing a semiconductor device with double structured well  
A semiconductor device includes a p-type silicon substrate, a first well of p-type formed in a major surface of the silicon substrate, and a second well of n-type formed close to the first well in...
5523247 Method of fabricating self-aligned planarized well structures  
A method of forming a planarized self-aligned integrated circuit structure suitable for forming CMOS circuitry is provided. The method involves using first and second barrier layers to define the...
5460984 Method of manufacturing a semi conductor device having a second well formed within a first well  
A method of manufacturing a semiconductor device including the steps of: forming an oxide film on the surface of a semiconductor substrate, and thereafter injecting ions of a first conductivity...
5411899 Transistor fabrication of a twin tub using angled implant  
A method for forming a twin tub semiconductor integrated circuit is disclosed. A portion of a semiconductor substrate is masked by oxide, nitride and photoresist. P-type dopant is directed towards...
5397734 Method of fabricating a semiconductor device having a triple well structure  
A method of fabricating a semiconductor device having a p-type semiconductor substrate and a p-well for memory cells which is formed in the substrate is disclosed. N-type impurities are implanted...
5372955 Method of making a device with protection from short circuits between P and N wells  
A method of manufacture of a MOSFET device with a predetermined light positive or negative doping comprises forming a first mask upon said substrate. Dopant of a predetermined positive or negative...
5256563 Doped well structure and method for semiconductor technologies  
A method of forming doped wells 24 and 30 in a semiconductor layer is disclosed herein. In a preferred embodiment, an oxide layer 16 is formed on the surface of a silicon layer 14. A nitride layer...
5252510 Method for manufacturing a CMOS device having twin wells and an alignment key region  
A method for manufacturing a CMOS semiconductor device having twin wells is disclosed. The method of manufacturing the CMOS device comprises the following. A silicon substrate is provided. A thick...
5252501 Self-aligned single-mask CMOS/BiCMOS twin-well formation with flat surface topography  
A single-mask self-aligned process is disclosed for formation of n and p wells for advanced CMOS and BiCMOS technologies. The proposed process forms n-well and p-well regions using a single...
5219783 Method of making semiconductor well structure  
A method of forming doped well regions in a semiconductor layer 14 is disclosed herein. At least one n-doped region 30 and at least one p-doped region 36 are formed in the semiconductor layer 14....
5192712 Control and moderation of aluminum in silicon using germanium and germanium with boron  
A process is disclosed for controlling the diffusion of aluminum in silicon for the fabrication of monolithic pn junction isolated integrated circuits. Germanium is incorporated into the silicon...
5151382 Method of manufacturing a semiconductor device by maskless pn junction isolation means  
A semiconductor body (1 ) is provided having a first region (4) of one conductivity type adjacent one major surface (2). An insulating layer (5) is formed on the one major surface and masking means...
5130271 Method of manufacturing a semiconductor device having no step at the boundary between self aligned p- or n- type impurity regions  
A method of manufacturing a semiconductor device includes the steps of forming an insulating film on a semiconductor substrate, selectively removing the insulating film to expose a surface of the...
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