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7629697 |
Marker structure and method for controlling alignment of layers of a multi-layered substrate
The invention includes a lithographic system having a first source for generating radiation with a first wavelength and an alignment system with a second source for generating radiation with a...
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7629223 |
Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device includes forming a plurality of trenches for element isolation and a plurality of trenches for alignment mark on a substrate. The substrate has an...
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7626278 |
Chip package
A chip package including a substrate, a chip and a mark is provided. The substrate has a carrying surface. A mark region is disposed on the carrying surface. The chip is disposed on the carrying...
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7618875 |
Marking method for product information
A product information marking method including a back side grinding step for grinding the back side of a wafer having a plurality of devices formed on the front side so as to be partitioned by a...
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7611961 |
Method for fabricating semiconductor wafer with enhanced alignment performance
A manufacturing method of a semiconductor wafer includes forming a plurality of alignment trenches in the wafer substrate. A dielectric layer is formed over the substrate filling the trenches. A...
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7611944 |
Integrated circuit fabrication
A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method...
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7611958 |
Method of making a semiconductor element
A method of producing a capacitor that includes producing a first electrode having a first surface; forming a recess in an element, walls of the element and the first surface of the first electrode...
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7611960 |
Method and system for wafer backside alignment
Disclosed is a method and a system for wafer backside alignment. A zero mark patterning on front side of a substrate. A plurality of layers are deposited on the front side of the substrate. The...
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7605016 |
CMOS image sensor and method of manufacturing the same
Disclosed are a CMOS sensor and a method of fabricating the CMOS sensor. The method includes the steps of: forming a first USG layer on an entire surface of a semiconductor substrate including a...
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7601605 |
Method for manufacturing semiconductor device, method for forming alignment mark, and semiconductor device
A method for manufacturing a semiconductor device includes the steps of: forming a first dielectric film on a substrate; etching the first dielectric film in a plug forming region to form a first...
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7602072 |
Substrate having alignment marks and method of obtaining alignment information using the same
The alignment marks formed in a scribe line of a semiconductor substrate include at least one main mark, a first sub-mark and second sub-marks. The first sub-mark is formed at a central portion of...
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7598024 |
Method and system for enhanced lithographic alignment
A method for alignment mark preservation includes a step of preparing a lower alignment mark structure on a substrate. In one configuration of the invention, the alignment mark structure includes a...
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7595251 |
Method of fabricating semiconductor device having alignment key and semiconductor device fabricated thereby
In a method of fabricating a semiconductor device having an alignment key and a semiconductor device fabricated thereby. The method of fabricating a semiconductor device includes providing a...
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7595258 |
Overlay vernier of semiconductor device and method of manufacturing the same
After a mother vernier pattern is formed in a scribe region of a semiconductor substrate, a child vernier pad is formed on the inner region of a mother vernier, and a child vernier is formed on the...
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7588993 |
Alignment for backside illumination sensor
An apparatus and manufacturing method thereof, wherein an integrated circuit is located in a first region of a substrate having first and second opposing major surfaces, and wherein an alignment...
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7585742 |
Semiconductor device manufacturing method
In a semiconductor device manufacturing method, a surface of a substrate structure including a semiconductor layer is covered with a first film including first and second openings. The first...
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7585708 |
Method for manufacturing a thin-film transistor
A thin-film transistor is formed on a transparent substrate and has a gate electrode film layer and a source and drain regions, and further has an alignment mark made of one and the same...
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7582538 |
Method of overlay measurement for alignment of patterns in semiconductor manufacturing
A method for semiconductor manufacturing includes forming an overlay target having a pattern formed by a first mask layer and an adjacent layer. The overlay target is exposed to radiation. As a...
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7583834 |
Laser etched fiducials in roll-roll display
The present invention relates to a method of aligning comprising providing a support, applying a transparent layer, patterning at least the transparent layer to produce a pattern and an alignment...
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7583284 |
Method for arranging print head chips
A method for arranging print head chips, includes: (a) setting a first fiducial mark and a second fiducial mark on a PCB for determining coordinate positions of a plurality of array units that are...
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7575980 |
Semiconductor device and method for manufacturing the same
A semiconductor device and a method manufacturing the same prevents copper from being exposed to a surface of a passivation film after a copper metal line formation, to avoid contamination of...
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7550362 |
Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device includes forming a sacrificial layer for forming a lower electrode as an amorphous carbon layer in order to prevent collapsing of a cylindrical...
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7550379 |
Alignment mark, use of a hard mask material, and method
In a method to produce an alignment mark, an oxide layer and sacrificial layer are processed to comprise recesses. The recesses are filled with a filler material. During filling the recesses, a...
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7547608 |
Polysilicon hard mask for enhanced alignment signal
A method is provided for forming a polysilicon layer on a substrate and aligning an exposure system with an alignment feature of the substrate through the polysilicon layer. In such method, a...
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7544581 |
Method for manufacturing display substrate
A method for manufacturing a display substrate is disclosed, which includes the following steps: providing a substrate; forming a plurality of bumps on an active area of the substrate and at least...
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7541256 |
Method of fabricating back-illuminated imaging sensors using a bump bonding technique
A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate, and resulting imaging device is disclosed. The method for manufacturing the...
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7534695 |
Method of manufacturing a semiconductor device
A semiconductor-device manufacturing method includes forming an element separating insulating film on a semiconductor substrate; forming a gate multilayer film for forming a gate electrode thereon;...
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7534637 |
Tunable alignment geometry
An alignment target with geometry designs provides a desired alignment offset for processes (both symmetric and asymmetric) on a wafer substrate. The alignment target includes one or more...
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7525201 |
Semiconductor chip having solder bumps and dummy bumps
A semiconductor chip comprises a silicon substrate on which semiconductor elements are formed, pads, each of which is formed on the silicon substrate and electrically connected to at least one of...
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7514278 |
Test-key for checking interconnect and corresponding checking method
A test key for checking an interconnect structure is described, including a contiguous metal line and multiple conductive plugs on the contiguous metal line, wherein one end of each plug contacts...
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7514802 |
Wiring board
A flexible insulating base, a plurality of conductor wirings aligned on the flexible insulating base, and bump electrodes provided respectively in end portions of the plurality of conductor wirings...
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7514305 |
Apparatus and methods for improving the intensity profile of a beam image used to process a substrate
Methods and apparatuses are provided for improving the intensity profile of a beam image used to process a semiconductor substrate. At least one photonic beam may be generated and manipulated to...
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7507633 |
Method and structure for improved alignment in MRAM integration
A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment...
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7504313 |
Method for forming plural kinds of wells on a single semiconductor substrate
A method is provided for forming plural kinds of wells on a single semiconductor substrate with an improved alignment accuracy and obviating the generation of step height between the wells. The...
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7494830 |
Method and device for wafer backside alignment overlay accuracy
A method for wafer backside alignment overlay accuracy includes forming a buried layer on a front-side of a wafer; forming a conductive layer on the buried layer and patterning a first test...
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7495347 |
Ion implantation with multiple concentration levels
A method that includes providing a semiconductor substrate having a mask on a surface thereof. The mask includes a first region having no masking elements and a second region having a plurality of...
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7494892 |
Method of measuring warpage of rear surface of substrate
A method of measuring warpage of a rear surface of a substrate includes a substrate detection step, a best fit plane calculation step, and a warpage calculation step. Further, the method of...
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7491620 |
Method and structures for indexing dice
A method of indexing a plurality of dice obtained from a material wafer comprising a plurality of stacked material layers, each die being obtained in a respective die position in the wafer, the...
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7488669 |
Method to make markers for double gate SOI processing
A method of making at least one marker (MX) for double gate SOI processing on a SOI wafer is disclosed. The marker has a diffracting structure in a first direction and the diffracting structure is...
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7485975 |
Alignment error measuring mark and method for manufacturing semiconductor device using the same
The object of the present invention is providing an alignment error measuring mark for an accurate alignment in a metal photolithography process. A substrate reference mark 110 is produced by...
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7482703 |
Semiconductor device having align mark layer and method of fabricating the same
A semiconductor device includes a pad electrode layer and an align mark layer, formed on the semiconductor substrate. A passivation layer is formed on the semiconductor substrate and exposes at...
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7473619 |
Method of fabricating semiconductor device having alignment key and semiconductor device fabricated thereby
In a method of fabricating a semiconductor device having an alignment key and a semiconductor device fabricated thereby. The method of fabricating a semiconductor device includes providing a...
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7465641 |
Method for manufacturing a semiconductor device
Manufacturing a semiconductor device by removing the insulation film in an alignment mark-forming region, depositing a first semiconductor layer, removing the insulation film on the semiconductor...
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7465604 |
Methods of fabricating alignment key structures in semiconductor devices including protected electrode structures
An integrated circuit device includes a storage cell including an upper electrode and a lower electrode on a substrate, and a conductive hard mask pattern directly on the upper electrode of the...
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7462548 |
Substrate provided with an alignment mark in a substantially transmissive process layer, mask for exposing said mark, device manufacturing method, and device manufactured thereby
A substrate provided with an alignment mark in a substantially transmissive process layer overlying the substrate, said mark comprising high reflectance areas for reflecting radiation of an...
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7459699 |
Method of determining processing position in charged particle beam apparatus, and infrared microscope used in the method
A laser mark which will be the positioning mark for a secondary charged particle image in the charged particle beam apparatus is applied by moving the sample processing/observation area in the...
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7456079 |
EPI wafer and method of making the same
A method including forming alignment marks in an upper surface of a semiconductor wafer; selectively depositing a mask over the alignment marks leaving portions of the upper surface exposed;...
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7456083 |
Semiconductor device and manufacturing method of the same
The invention is directed to an improvement of cutting accuracy in a cutting process when a semiconductor device attached with a supporting member is manufactured. The invention provides a...
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7449790 |
Methods and systems of enhancing stepper alignment signals and metrology alignment target signals
Methods and systems of enhancing stepper alignment signals and metrology alignment target signals. In one embodiment, a plurality of alternating rows comprising a first material of a first height...
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7449792 |
Pattern registration mark designs for use in photolithography and methods of using the same
Pattern registration marks which include: a substrate and an upper material layer disposed above the substrate; an outer trench formed in the upper material layer, the outer trench having an outer...
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