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9040382 Selective epitaxial growth of semiconductor materials with reduced defects  
A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and...
9029954 Semiconductor device and manufacturing method therefor  
A semiconductor device according to the present invention has an n-type MIS transistor. The n-type MIS transistor has a first active region surrounded by a device isolation region in a...
9023713 Ultrathin body fully depleted silicon-on-insulator integrated circuits and methods for fabricating same  
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing an ultrathin body (UTB) fully...
9023704 Method for fabricating a semiconductor device  
A method for fabricating a semiconductor device includes forming a pre-isolation layer covering a fin formed on a substrate, the pre-isolation layer including a lower pre-isolation layer making...
9023712 Method for self-aligned removal of a high-K gate dielectric above an STI region  
By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure...
9018046 Area-efficient distributed device structure for integrated voltage regulators  
An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler...
9012300 Manufacturing method for a shallow trench isolation  
A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one...
9000518 Semiconductor device and related fabrication methods  
Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first vertical drift region of semiconductor material, a second...
8994117 Moat construction to reduce noise coupling to a quiet supply  
A semiconductor chip having a P− substrate and an N+ epitaxial layer grown on the P− substrate is shown. A P− circuit layer is grown on top of the N+ epitaxial layer. A first moat having an...
8987111 Method of manufacturing a three dimensional array having buried word lines of different heights and widths  
According to a method of fabricating a semiconductor device, a first mask pattern is used to etch first device isolation layers and active lines or form grooves, in which word lines will be...
8987100 Method of fabricating fin-field effect transistors (finfets) having different fin widths  
Provided are methods of forming field effect transistors. The method includes preparing a substrate with a first region and a second region, forming fin portions on the first and second regions,...
8987093 Multigate finFETs with epitaxially-grown merged source/drains  
Method of forming multi-gate finFETs with epitaxially-grown merged source/drains. Embodiments of the invention may include forming a plurality of semiconductor fins joined by a plurality of...
8975154 Process for producing at least one deep trench isolation  
A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor...
8957496 Integrated circuit chip with discontinuous guard ring  
An electronic apparatus includes a semiconductor substrate, a circuit block disposed in and supported by the semiconductor substrate and comprising an inductor, and a discontinuous noise isolation...
8946048 Method of fabricating non-volatile memory with flat cell structures and air gap isolation  
High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between...
8936993 Hybrid substrate with improved isolation and simplified method for producing a hybrid substrate  
A hybrid substrate comprises first and second active areas made from semiconductor materials laterally offset from one another and separated by an isolation area. The main surfaces of the...
8936994 Method of processing a substrate in a lithography system  
A method of processing substrates in a lithography system unit, the lithography system unit comprising at least two substrate preparation units, a load lock unit comprising at least first and...
8927373 Methods of fabricating non-planar transistors including current enhancing structures  
Methods of fabricating non-planar transistors including current enhancing structures are provided. The methods may include forming first and second fin structures directly adjacent each other...
8927374 Semiconductor device and fabrication method thereof  
A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained...
8927362 CMOS device and method of forming the same  
A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The...
8900974 High yield substrate assembly  
High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback...
8895403 Transistor, method for fabricating the transistor, and semiconductor device comprising the transistor  
A transistor, a method for fabricating a transistor, and a semiconductor device comprising the transistor are disclosed in the present invention. The method for fabricating a transistor may...
8895369 Methods for manufacturing superjunction semiconductor device having a dielectric termination  
A superjunction semiconductor device is provided having at least one column of a first conductivity type and at least one column of a second conductivity type extending from a first main surface...
8883607 Full wafer processing by multiple passes through a combinatorial reactor  
Overlapping combinatorial processing can offer more processed regions, better particle performance and simpler process equipment. In overlapping combinatorial processing, one or more regions are...
8883578 Strained silicon nFET and silicon germanium pFET on same wafer  
Various embodiments form silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is obtained. The semiconductor wafer comprises a substrate, a...
8877601 Lateral capacitor and method of making  
An active device region is formed in and on a semiconductor substrate. An interconnect layer is formed over the active device region, wherein the interconnect layer comprises a first dielectric...
8865560 FinFET design with LDD extensions  
System and method for forming lightly doped drain (LDD) extensions. An embodiment comprises forming a gate electrode on a semiconductor fin and forming a dielectric layer over the gate electrode....
8865561 Back-gated substrate and semiconductor device, and related method of fabrication  
A method of forming a semiconductor device is disclosed. The method includes forming a set of doped regions in a substrate; forming a crystalline dielectric layer on the substrate, the crystalline...
8859375 High voltage device and manufacturing method thereof  
The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes...
8853051 Methods of recessing an active region and STI structures in a common etch process  
Generally, the present disclosure is directed to various methods of recessing an active region and an adjacent isolation structure in a common etch process. One illustrative method disclosed...
8847195 Structures for resistance random access memory and methods of forming the same  
Memory cells and methods of forming the same and devices including the same. The memory cells have first and second electrodes. An amorphous semiconductor material capable of electronic switching...
8841178 Strained silicon nFET and silicon germanium pFET on same wafer  
Various embodiments form silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is obtained. The semiconductor wafer comprises a substrate, a...
8835275 Semiconductor devices having nitrided gate insulating layer and methods of fabricating the same  
Semiconductor devices, and methods of fabricating the same, include forming device isolation regions in a substrate to define active regions, forming gate trenches in the substrate to expose the...
8828839 Methods for fabricating electrically-isolated finFET semiconductor devices  
Fabrication methods for semiconductor device structures are provided. In an exemplary embodiment, a method of fabricating an electrically-isolated FinFET semiconductor device includes the steps of...
8828489 Homogeneous modification of porous films  
Porous films are homogeneously and partially (but not completely) filled. A composition (that includes a polymer) is brought into contact with a planar film that has interconnected pores...
8828882 Method for forming a deep trench in a microelectronic component substrate  
A trench is formed in a semiconductor substrate by depositing an etch mask on the substrate having an opening, etching of the trench through the opening, and doping the walls of the trench. The...
8815699 Fabrication of reverse shallow trench isolation structures with super-steep retrograde wells  
Generally, the present disclosure is directed to methods for forming reverse shallow trench isolation structures with super-steep retrograde wells for use with field effect transistor elements....
8815698 Well region formation method and semiconductor base  
A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate...
8796126 Method of manufacturing semiconductor device  
A method of manufacturing a semiconductor device includes forming an insulating isolation portion in a groove of a substrate, forming a projection portion in which an upper portion of the...
8796105 Method and apparatus for preparing polysilazane on a semiconductor wafer  
A method for depositing a polysilazane on a semiconductor wafer is provided. The method includes steps of disposing a silazane onto the semiconductor wafer, and heating the silazane to form the...
8785290 Method for manufacturing semiconductor device having element isolation portions  
A method for manufacturing a semiconductor device, the method comprising, forming an opening in an insulating layer, which is formed on a semiconductor substrate, using a photoresist pattern...
8778771 Semiconductor device, method of manufacturing the same, and solid-state image sensor  
A method of manufacturing a semiconductor device includes steps of providing a substrate including a semiconductor portion, a non-porous semiconductor layer, and a porous semiconductor layer...
8772124 Full wafer processing by multiple passes through a combinatorial reactor  
Overlapping combinatorial processing can offer more processed regions, better particle performance and simpler process equipment. In overlapping combinatorial processing, one or more regions are...
8772130 Manufacturing method of SOI substrate  
In order to keep the crystallinity of the semiconductor thin film layer high, a temperature of a semiconductor substrate during hydrogen ion addition treatment is suppressed to lower than or equal...
8748275 Semiconductor devices comprising a channel semiconductor alloy formed with reduced STI topography  
In sophisticated semiconductor devices, a semiconductor alloy, such as a threshold adjusting semiconductor material in the form of silicon/germanium, may be provided in an early manufacturing...
8748256 Integrated circuit having silicide block resistor  
A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a...
8741733 Stress in trigate devices using complimentary gate fill materials  
Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the...
8735254 Manufacture method of a high voltage MOS semiconductor device  
A semiconductor device has: a low concentration drain region creeping under a gate electrode of a MIS type transistor; a high concentration drain region having an impurity concentration higher...
8735259 Method of producing insulation trenches in a semiconductor on insulator substrate  
A method for producing one or plural trenches in a device comprising a substrate of the semiconductor on insulator type formed by a semiconductive support layer, an insulating layer resting on the...
8728903 Semiconductor device having an oxide film formed on a semiconductor substrate sidewall of an element region and on a sidewall of a gate electrode  
A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a...
Matches 1 - 50 out of 356 1 2 3 4 5 6 7 8 >