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7615457 Method of fabricating self-aligned bipolar transistor having tapered collector  
A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted...
7611955 Method of forming a bipolar transistor and semiconductor component thereof  
A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor...
7521327 High fT and fmax bipolar transistor and method of making same  
A high f T and f max bipolar transistor includes an emitter, a base, and a collector. The emitter has a lower portion and an upper portion that extends beyond the lower portion. The base includes...
7491617 Transistor structure with minimized parasitics and method of fabricating the same  
A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion...
7397070 Self-aligned transistor  
In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor.
7396723 Method of manufacturing EEPROM device  
A method of manufacturing an EEPROM device can reduce the cell area. The method of manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) includes forming a mask pattern over...
7338875 Method of fabricating a semiconductor device having a toroidal-like junction  
Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints...
7300850 Method of forming a self-aligned transistor  
In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor.
7288829 Bipolar transistor with self-aligned retrograde extrinsic base implant profile and self-aligned silicide  
Disclosed is a method of forming a transistor in an integrated circuit structure that begins by forming a collector in a substrate and an intrinsic base above the collector. Then, the invention...
7259050 Semiconductor device and method of making the same  
A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer...
7232732 Semiconductor device with a toroidal-like junction  
Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints...
7169677 Method for producing a spacer structure  
A method for fabricating a spacer structure includes: forming a gate insulation layer having a gate deposition-inhibiting layer, a gate layer and a covering deposition-inhibiting layer on a...
7118981 Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor  
In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by...
7105415 Method for the production of a bipolar transistor  
The invention relates to a method for producing a bipolar transistor. A semiconductor substrate is provided that encompasses a collector area of a first conductivity type, which is embedded therein...
7094636 Method of forming a conductive line  
A method of forming a conductive line includes forming conductive material received over a semiconductor substrate into a line having opposing sidewalls. Insulative material is deposited over the...
7084028 Semiconductor device and method of manufacturing a semiconductor device  
A semiconductor device comprises a semiconductor substrate having a cavity region inside; a first insulation film formed on the inner wall of the cavity region; a first electrode formed on the...
7005359 Bipolar junction transistor with improved extrinsic base region and method of fabrication  
A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer...
6943077 Selective spacer layer deposition method for forming spacers with different widths  
A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a...
6924202 Heterojunction bipolar transistor with self-aligned emitter and sidewall base contact  
A heterojunction bipolar transistor (HBT), and manufacturing method therfor, comprising a semiconductor substrate having a collector region is provided. A base contact layer is formed over the...
6911368 Arrangement for preventing short-circuiting in a bipolar double-poly transistor and a method of fabricating such an arrangement  
In a bipolar double-poly transistor comprising a layer of base silicon ( 1 ′) on a silicon substrate ( 2 ′), a first layer of silicon dioxide ( 3 ′) on the base silicon layer ( 1 ′), an...
6900519 Diffused extrinsic base and method for fabrication  
The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present...
6887765 Method for manufacturing a bipolar junction transistor  
According to one embodiment of the invention, a method used in manufacturing an intermediate structure in a bipolar junction transistor includes implanting a base dopant in a semiconductor...
6867105 Bipolar transistor and method of fabricating a bipolar transistor  
A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter...
6861325 Methods for fabricating CMOS-compatible lateral bipolar junction transistors  
A method for fabricating a lateral bipolar junction transistor in an active area of a substrate includes forming a base structure directly on a central portion of the active area without a gate...
6846716 Integrated circuit device and method therefor  
A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although...
6830967 Method for forming CMOS transistor spacers in a BiCMOS process  
According to an exemplary method in one embodiment, a transistor gate is fabricated on a substrate. Next, an etch stop layer may be deposited on the substrate. The etch stop layer may, for example,...
6818492 Semiconductor device and manufacturing method thereof  
This invention provides a semiconductor device which is excellent in high-frequency characteristics, wherein emitter diffusion is performed by a trench formed in a base region, the base resistance...
6797579 Semiconductor device having trench isolation structure and method of fabricating the same  
A semiconductor device having a trench isolation structure and a method of fabricating the same are provided. The device has a trench region and an isolation structure. The trench region is...
6784065 Bipolar transistor with ultra small self-aligned polysilicon emitter and method of forming the transistor  
A low-power bipolar transistor is formed to have an intrinsic emitter region with a sub-lithographic width, and an oxide layer that is self aligned to an overlying extrinsic emitter. The small...
6774002 Structure and method for forming self-aligned bipolar junction transistor with expitaxy base  
The present invention proposes a novel method to fabricate a Bipolar Junction Transistor device. The steps of the present invention include forming a shallow trench isolation structure in a...
6764893 Method for reducing a parasitic capacitance of a semiconductive memory cell using metal mask for sidewall formation  
The present invention provides a method for reducing loading capacitance. The inventive method includes the steps of: forming a plurality of patterns on a substrate, wherein the patterns are formed...
6727155 Method for spin etching sidewall spacers by acid vapor  
A method forming sidewall spacers on a semiconductor substrate without using the conventional plasma etching method is disclosed. In the method, a semiconductor substrate that has a gate structure...
6720226 Semiconductor device and method for facticating the same  
Gate insulating film, gate electrode made up of lower and upper gate electrodes, and on-gate passivation film are formed in this order on an Si substrate. Then, a sidewall is formed as a stack of...
6713361 Method of manufacturing a bipolar junction transistor including undercutting regions adjacent to the emitter region to enlarge the emitter region  
According to one embodiment of the invention, a method for manufacturing bipolar junction transistors includes disposing a first oxide layer between a semiconductor substrate and a base polysilicon...
6686251 Method for fabricating a bipolar transistor having self-aligned emitter and base  
A method for forming a self-aligned bipolar transistor includes the steps of combination etching a silicon substrate in an opening to form a concave surface on the silicon substrate, and forming an...
6661055 Transistor in semiconductor devices  
The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. According to the present invention, the transistor has an auxiliary electrode to which...
6642119 Silicide MOSFET architecture and method of manufacture  
The present invention relates to a method of forming a transistor and a transistor structure. The invention comprises forming the transistor using a double silicide process which reduces resistance...
6627504 Stacked double sidewall spacer oxide over nitride  
Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by recessing the silicon nitride spacers and forming barrier...
6624034 Method of making field effect transistor in which the increase of parasitic capacitance is restrained by scale reduction  
A method of producing a semiconductor device includes forming a gate electrode on a channel region on a surface of a semiconductor region of a semiconductor substrate, the channel region having a...
6610571 Approach to prevent spacer undercut by low temperature nitridation  
A new method is provided for the removal of liner oxide from the surface of a gate electrode during the creation of the gate electrode. A layer of gate oxide is formed over the surface of a...
6607961 Method of definition of two self-aligned areas at the upper surface of a substrate  
A method for defining, on the upper surface of a substrate, two self-aligned areas, including the steps of depositing a protective layer; depositing a covering layer; opening the protective and...
6479362 Semiconductor device with high-temperature-stable gate electrode for sub-micron applications and fabrication thereof  
An improved gate electrode provides greater tolerances to higher temperature annealing treatments, and is useful in connection with the formation of self-aligned contacts as are needed for high...
6465317 Process for producing a bipolar transistor with self-aligned emitter and extrinsic base  
A transistor manufacturing process includes the formation, on a layer ( 15 ) that will form the base of the transistor, of a stack of an SiGe alloy layer ( 16 ), a silicon oxide layer ( 17 ) and a...
6458667 High power PMOS device  
An improved MOS transistor and method for making it are described. The MOS transistor's source and drain have a first conductivity type and are separated from each other by a first region having a...
6436783 Method of forming MOS transistor  
(issue) It is an issue to suppress variation in threshold voltage due to deterioration in shot channel characteristics and improve the slow trap characteristics of the MOS transistor for...
6436782 Process for fabricating a self-aligned double-polysilicon bipolar transistor  
The process includes successively forming, over a base region of a semiconductor substrate, a poly-Ge or poly-SiGe layer, an etch-stop layer over a selected zone of the Ge or SiGe layer, a layer of...
6436781 High speed and low parasitic capacitance semiconductor device and method for fabricating the same  
A semiconductor device including a bipolar transistor formed by epitaxial growth or ion implantation is provided has an epitaxial silicon collector layer, a base region directly under an emitter...
6399452 Method of fabricating transistors with low thermal budget  
A low thermal budget transistor is fabricated by first forming a gate on a semiconductor substrate. First amorphous regions and first inactive dopant regions are then created in the substrate by...
6368946 Manufacture of a semiconductor device with an epitaxial semiconductor zone  
A method of manufacturing a semiconductor device with an epitaxial semiconductor zone, whereby a first layer of insulating material, a first layer of non-monocrystalline silicon, and a second...
6365451 Transistor and method  
A method of fabricating a semiconductor device and the device. The device is fabricated by providing a substrate having a region thereover of electrically conductive material, and a dielectric...
Matches 1 - 50 out of 165 1 2 3 4 >