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5516709 Method of manufacturing bipolar transistor with reduced numbers of steps without increasing collector resistance  
A method of manufacturing a bipolar transistor including the steps of doping an impurity of the one conductivity type in a major surface portion of the semiconductor substrate to form a buried...
5516710 Method of forming a transistor  
A method is provided for forming a transistor for a bipolar, CMOS, or bipolar CMOS integrated circuit. The method is applicable to forming a double polysilicon self-aligned bipolar transistor...
5491105 LDMOS transistor with self-aligned source/backgate and photo-aligned gate  
An embodiment of the present invention is a method of fabricating power and non-power devices on a semiconductor substrate, the method comprising: forming alignment marks in the substrate (100);...
5488003 Method of making emitter trench BiCMOS using integrated dual layer emitter mask  
A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base...
5480815 Method of manufacturing a biopolar transistor in which an emitter region is formed by impurities supplied from double layered polysilicon  
A process of fabricating a bipolar transistor, particularly forming a very shallow, uniform emitter diffused-layer for the purpose of realizing a higher speed of the device without need of...
5480816 Method of fabricating a bipolar transistor having a link base  
On an epitaxial layer (4) serving as a collector layer are formed an emitter layer (10), an intrinsic base layer (9) surrounding the emitter layer (10) while permitting the surface of the emitter...
5455185 Method for manufacturing a bipolar transistor having base and collector in a vertical sequence  
In an epitaxial layer (3) deposited on a substrate (1), emitter (14), base (6) and collector (15) are disposed in a vertical sequence in such a way that the emitter (14) adjoins the surface of the...
5416032 Method of making a high conductivity p-plus region for self-aligned, shallow diffused, bipolar transistors  
According to the present invention, using an emitter-P+ (E-P) mask, a low resistance, high conductivity P+ region of a self-aligned bipolar transistor device is formed prior to the formation of a...
5407857 Method for producing a semiconductor device with a doped polysilicon layer by updiffusion  
There is provided a semiconductor device wherein a resistor layer is interposed between a semiconductor region and a surface electrode metal so as to improve a safe operation area of the device...
5399526 Method of manufacturing semiconductor device by forming barrier metal layer between substrate and wiring layer  
A method of manufacturing a semiconductor device which comprises steps of forming a diffusion region to a semiconductor substrate; forming silicon compound film on the diffusion region; forming a...
5340753 Method for fabricating self-aligned epitaxial base transistor  
The present invention is directed to a method for forming a self-aligned epitaxial base transistor in a double polysilicon type process using non-selective low temperature epitaxy (LTE) to form...
5298462 Method of making metallization for semiconductor device  
In a semiconductor device including a semiconductor body, a continuous oxide layer, a continuous metallization layer, and a diffusion zone, the diffusion zone is located below a portion of the...
5296391 Method of manufacturing a bipolar transistor having thin base region  
A method of manufacturing a semiconductor device includes a monocrystalline semiconductor layer of one conductivity type with a first insulating film covering the semiconductor layer. An aperture...
5227318 Method of making a cubic boron nitride bipolar transistor  
A bipolar transistor is formed from epitaxial cubic boron nitride grown on a silicon substrate which is a three to two commensurate layer deposited by pulsed laser evaporation techniques. The thin...
5219767 Process for preparing semiconductor device  
Disclosed is a process for preparing a semiconductor device which comprises a step of growing, in a molecular beam epitaxial growth apparatus, a P-type silicon epitaxial layer which becomes the...
5200347 Method for improving the radiation hardness of an integrated circuit bipolar transistor  
A method is provided for use with an integrated circuit which includes a npn bipolar transistor on which a variable thickness oxide layer has been formed, the method for improving the radiation...
5185276 Method for improving low temperature current gain of bipolar transistors  
A method for improving the low temperature current gain of silicon bipolar transistors by implanting a first and a second impurity of the same conductivity type into the base region to provide a...
5177025 Method of fabricating an ultra-thin active region for high speed semiconductor devices  
A method of fabricating a semiconductor device to retard diffusion of a dopant from a center active region into adjacent regions. The center active region is epitaxially formed by selectively...
5114867 Sub-micron bipolar devices with method for forming sub-micron contacts  
The sub-micron bipolar devices with method for forming sub-micron contacts provides a sub-micron bipolar device and process for manufacturing it with contacts down to 0.1 microns or less. All...
5087578 Semiconductor device having multi-layered wiring  
A semiconductor device comprises a first electrode provided on a semiconductor substrate, and constituting a lower wiring layer, an insulating layer provided on the first electrode and the...
5024957 Method of fabricating a bipolar transistor with ultra-thin epitaxial base  
A method of forming a bipolar transistor is provided, comprising the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming a layer of...
4999318 Method for forming metal layer interconnects using stepped via walls  
A method for forming vias, interconnecting selected wiring layers of an integrated circuit device, which overcomes oxide formation on the wiring metal surface which is exposed at the etched via...
4971929 Method of making RF transistor employing dual metallization with self-aligned first metal  
An improved dual metallization process in which self-aligned tungsten contacts are formed to closely-spaced emitter or source sites in RF power silicon devices. Low-resistivity ohmic contacts are...
4945394 Bipolar junction transistor on silicon carbide  
The invention comprises a bipolar junction transistor formed in silicon carbide. By utilizing high temperature ion implantation of doping ions, the base and emitter can be formed as wells,...
4927773 Method of minimizing implant-related damage to a group II-VI semiconductor material  
A method of forming in a semiconductor material a region having a different chemical composition or a different concentration than a chemical composition or concentration of material surrounding...
4837177 Method of making bipolar semiconductor device having a conductive recombination layer  
A semiconductor device having a conductive recombination layer. The conductive recombination layer, comprised of doped polycrystalline material, doped polycrystalline material and tungsten...
4792534 Method of manufacturing a semiconductor device involving sidewall spacer formation  
A method of manufacturing a semiconductor device having a submicron pattern. A p-type semiconductor layer is formed on an n-type semiconductor substrate. Insulating films are formed on the p-type...
4717588 Metal redistribution by rapid thermal processing  
A method for diffusing a metal dopant into a semiconductor switching device is provided by the use of a rapid thermal heating apparatus. This method provides a procedure for the selectively...
4709469 Method of making a bipolar transistor with polycrystalline contacts  
Disclosed herein is a semiconductor device manufacturing process applicable to a bipolar semiconductor integrated circuit device in which a base electrode (9) is directly extracted from an active...
4678537 Method of manufacturing semiconductor devices  
To reduce the parasitic capacitance due to the graft base area in a transistor device and to miniaturize the device, the graft base area is connected to a conductive layer to be connected to the...
4631560 MOMS tunnel emission transistor  
An MOMS tunnel emission transistor is provided by a plurality of mesa stacked horizontal layers including at least one semiconductor layer (63) having an exposed edge (68) at a generally vertical...
4573256 Method for making a high performance transistor integrated circuit  
A process for making high performance NPN bipolar transistors functioning in a current switch logic circuit. A bipolar transistor is formed within an isolated region of a monocrystalline silicon...
4242693 Compensation of VBE non-linearities over temperature by using high base sheet resistivity devices  
In a transistor circuit a linear relationship between VBE and temperature is obtained by using high base sheet resistivity devices, such as super beta NPN transistors, or lateral PNP transistors....
4183780 Photon enhanced reactive ion etching  
A method and apparatus for modifying a surface, by either plasma etching the surface or plasma depositing a material thereon, by using vacuum ultraviolet radiation to control the modification of...
4179312 Formation of epitaxial layers doped with conductivity-determining impurities by ion deposition  
A method and apparatus for depositing a monocrystalline epitaxial layer of semiconductor material, e.g., silicon containing selected conductivity-determining impurities, on a semiconductor...
4151009 Fabrication of high speed transistors by compensation implant near collector-base junction  
A high speed bipolar transistor is obtained by the use of ion implanted compensating impurities into the base region near the collector-base junction. This compensating implant significantly...
4125415 Method of making high voltage semiconductor structure  
A semiconductor p-n junction structure with improved blocking voltage capability. The improvement results from the addition of a doped layer with limited total doping to the main p-n junction....
4114254 Method for manufacture of a semiconductor device  
A semiconductor device and method of making the same is disclosed having a surface passivation film of a polycrystalline silicon layer containing 2 to 45 atomic percent of oxygen atoms.The...
4105476 Method of manufacturing semiconductors  
Method of fabricating a high voltage (VCED = 800 volts) PNP Power Transistor by a triple diffusion technique.
4053925 Method and structure for controllng carrier lifetime in semiconductor devices  
The device structure is a bi-polar transistor having a region of inert atoms located in the collector adjacent to the base-collector junction. Another embodiment of the invention is a...
3999282 Method for manufacturing semiconductor devices having oxide films and the semiconductor devices manufactured thereby  
A silicon crystal body having a major surface lying parallel to a {110} or {100} crystal plane is prepared. A silicon oxide film is formed on the major surface by heating the body in an atmosphere...
3926695 Etched silicon washed emitter process  
This relates to a shallow diffused washed emitter process. Prior to diffusion of an emitter into the base region of an active element, a portion of the surface base region is etched away. During...
3866312 Method of contacting semiconductor regions in a semiconductor body  
A method of contacting internested semiconductor regions in a semiconductor body comprises removing, from the surface of the semiconductor body at which the semiconductor regions are formed, an...
3765961 SPECIAL MASKING METHOD OF FABRICATING A PLANAR AVALANCHE TRANSISTOR  
An avalanche junction transistor is fabricated by growing on an n+-type substrate an n-type epitaxial layer, masking all but a central region of the epitaxial layer, converting the central region...
3763550 GEOMETRY FOR A PNP SILICON TRANSISTOR WITH OVERLAY CONTACTS  
A semiconductor device having an expanded guard ring overlying substantially the entire surface of a region except for at least one island therein. A relatively thin protective coating overlies...
3753802 TRANSISTOR  
A method of making a transistor by forming a layer of high resistivity on a semiconductor collector body, diffusing a base zone into the layer to a depth less than the thickness of the layer and...
3660171 METHOD FOR PRODUCING SEMICONDUCTOR DEVICE UTILIZING ION IMPLANTATION  
A method for producing a transistor structure utilizing ion implantation, comprising the steps of implanting ions of base-forming impurity into a predetermined portion of a surface of a...
3639815 EPI BASE HIGH-SPEED POWER TRANSISTOR  
A transistor having an epitaxially grown base region has the good secondary breakdown voltage performance of a single diffused transistor having a base region comprising suitably doped material...
3551220 METHOD OF PRODUCING A TRANSISTOR  
3535774 METHOD OF FABRICATING SEMICONDUCTOR DEVICES