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7608873 Buried-gated photodiode device and method for configuring and operating same  
A 3-T buried-gated photodiode device that is suitable for use in a windowed array. The 3-T buried-gated photodiode device is configured such that the floating diffusion (FD) node of the device is...
7598160 Method for manufacturing thin film semiconductor  
A method for manufacturing thin film semiconductor device is provided. The semiconductor thin film includes a semiconductor thin film and a gate electrode and has an active region turned into a...
7566615 Methods of fabricating scalable two transistor memory devices  
A memory device includes a semiconductor substrate, a first gate insulator on a first portion of a semiconductor substrate, a storage node on the first gate insulator, a tunnel junction barrier on...
7547956 Thick oxide P-gate NMOS capacitor for use in a low-pass filter of a circuit and method of making same  
A circuit with dielectric thicknesses is presented that includes a low-pass filter including one or more semiconductor devices having a thick gate oxide layer, while further semiconductor devices...
7547606 Semiconductor device and method of manufacturing the same  
An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a gate insulation layer on a semiconductor substrate; forming a...
7524715 Memory cell transistor having different source/drain junction profiles connected to DC node and BC node and manufacturing method thereof  
A memory cell transistor of a DRAM device is provided. A gate stack pattern is formed on a semiconductor substrate. A DC node and a BC node are formed substantially under lateral sides of the gate...
7514307 Method of manufacturing a semiconductor apparatus  
A method of manufacturing a semiconductor apparatus of the present invention comprises forming body diffusion layer, a gate electrode, and an interlayer dielectric over an surface of a...
7501322 Methods of forming non-volatile memory devices having trenches  
A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective...
7485905 Electrostatic discharge protection device  
An electrostatic discharge protection device comprising a multi-finger gate, a first lightly doped region of a second conductivity, a first heavily doped region of the second conductivity, and a...
7439563 High-breakdown-voltage semiconductor device  
A high-breakdown-voltage semiconductor device comprises a high-resistance semiconductor layer, trenches formed on the surface thereof in a longitudinal plane shape and in parallel, first regions...
7402451 Optimized transistor for imager device  
An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a single (i.e, one-sided) active area...
7399669 Semiconductor devices and methods for fabricating the same including forming an amorphous region in an interface between a device isolation layer and a source/drain diffusion layer  
Semiconductor devices and methods for fabricating the same are disclosed in which an amorphous layer is formed in an interface between a device isolation layer and a source or drain region to...
RE40138 Method for improving hot carrier lifetime via a nitrogen implantation procedure performed before or after a Teos liner deposition  
A process for fabricating input/output, N channel, (I/O NMOS) devices, featuring an ion implanted nitrogen region, used to reduce hot carrier electron, (HEC), injection, has been developed. The...
7294551 Semiconductor device and method for manufacturing the same  
A semiconductor device has a gate electrode formed on a P type semiconductor substrate via gate oxide films. A first low concentration (LN type) drain region is made adjacent to one end of the gate...
7220646 Integrated circuit structure with improved LDMOS design  
A semiconductor integrated circuit including an LDMOS device structure comprises a semiconductor layer with a pair of spaced-apart field effect gate structures over an upper surface of the...
7211482 Method of forming a memory cell having self-aligned contact regions  
A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the...
7208385 LDMOS transistor with enhanced termination region for high breakdown voltage with on-resistance  
A structure for making a LDMOS transistor ( 100 ) includes an interdigitated source finger ( 26 ) and a drain finger ( 21 ) on a substrate ( 15 ). Termination regions ( 35, 37 ) are formed at the...
7202134 Method of forming transistors with ultra-short gate feature  
A gate electrode is formed over but insulated from a semiconductor body region for each of first and second transistors. A DDD implant is carried out to from DDD source and DDD drain regions in the...
7189623 Semiconductor processing method and field effect transistor  
A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate...
7172933 Recessed polysilicon gate structure for a strained silicon MOSFET device  
A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features...
7084039 Method of fabricating MOS transistor  
A method of fabricating a CMOS (complementary metal oxide semiconductor) transistor includes manufacturing steps, by which adverse transistor characteristics can be prevented from being degraded by...
7074658 Structure for an LDMOS transistor and fabrication method for thereof  
A structure for an LDMOS transistor has a horseshoe-shaped gate layer formed on a N-type layer of a semiconductor silicon substrate, in which the gate layer comprises a transverse-extending area, a...
7060581 Method for manufacturing a semiconductor device  
A method for manufacturing a semiconductor device, includes forming a first impurity implanted layer in a semiconductor substrate by selectively implanting ions of a first impurity. A dummy pattern...
7060580 Field effect transistor and method of fabricating the same  
Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming...
7041583 Method of removing features using an improved removal process in the fabrication of a semiconductor device  
A method for improving the etch behavior of disposable features in the fabrication of a semiconductor device is disclosed. The semiconductor device comprises a bottom anti-reflective coating layer...
7022565 Method of fabricating a trench capacitor of a mixed mode integrated circuit  
A method of fabricating a trench capacitor of a mixed mode integrated circuit includes forming shallow trench isolation regions for isolating active/passive devices on a semiconductor substrate....
7022577 Method of forming ultra shallow junctions  
The present invention relates to a method of fabricating a semiconductor device. In specific embodiments, the method comprises providing a semiconductor substrate, and ion implanting dopant...
7001818 MIS semiconductor device and manufacturing method thereof  
By suppressing a short-channel effect of a MIS field-effect transistor and reducing a fringing capacitance of a gate, a signal delay in the transistor can be shortened. The MIS field-effect...
6987052 Method for making enhanced substrate contact for a semiconductor device  
A method of forming a semiconductor structure in a semiconductor wafer includes the steps of forming an epitaxial layer on at least a portion of a semiconductor substrate of a first conductivity...
6974730 Method for fabricating a recessed channel field effect transistor (FET) device  
A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain...
6913980 Process method of source drain spacer engineering to improve transistor capacitance  
A method of forming an associated transistor is presented whereby short channel effects and junction capacitances are mitigated and enhanced switching speeds are thereby facilitated. Compensation...
6884688 Method for producing a MOS transistor and MOS transistor  
A MOS transistor includes a drain zone, a source zone, and a gate electrode. Doping atoms of the first conductivity type are implanted in the region of the drain zone and the source zone by at...
6867106 Semiconductor device and method for fabricating the same  
The semiconductor device comprises: a conducting layer including: a channel region; a source region and a drain region sandwiching the channel region; and a body region connected to the channel...
6849516 Methods of forming drain/source extension structures of a field effect transistor using a doped high-k dielectric layer  
According to one illustrative embodiment of the present invention, a method of forming a field effect transistor includes the formation of a doped high-k dielectric layer above a substrate...
6830978 Semiconductor device and manufacturing method for the same  
On a semiconductor substrate having a gate electrode and an LDD layer formed thereon, an SiN film to be a silicide block is formed. An opening communicating with the LDD layer is provided for the...
6828204 Method and system for compensating for anneal non-uniformities  
A method and system can compensate for anneal non-uniformities by implanting dopant in a pattern to provide higher dopant concentrations where the anneal non-uniformities result in lower active...
6818516 Selective high k dielectrics removal  
A method of forming a gate structure in an integrated circuit on a substrate. A high k layer is formed on the substrate, and a gate electrode layer is formed on the high k layer. The gate electrode...
6806155 Method and system for scaling nonvolatile memory cells  
A method and system for providing a semiconductor device are described. The method and system include providing a plurality of gate stacks and a first source drain halo implant. The first source...
6803287 Method for forming a semiconductor device having contact wires of different sectional areas  
In a semiconductor device ( 10 ), plural diffusion layer areas ( 2, 3 ) are formed so that the impurity concentration of the diffusion layer area ( 2 ) is set to be higher than that of the...
6800536 Semiconductor device having an insulated gate and a fabrication process thereof  
A semiconductor device includes a T-shaped gate on a gate insulation film, wherein the T-shaped gate includes a lower polycrystal layer containing Si and Ge and an upper polycrystal layer of...
6773971 Method of manufacturing a semiconductor device having lightly-doped drain (LDD) regions  
There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered...
6764912 Passivation of nitride spacer  
The formation of metal silicides in silicon nitride spacers on a gate electrode causes bridging between a gate electrode and the source and drain regions of a semiconductor device. The bridging is...
6762105 Short channel transistor fabrication method for semiconductor device  
The method comprising sequentially forming a first oxide film, a first nitride film, a second oxide film and a second nitride film on a semiconductor substrate; forming a first mask on the second...
6750159 Semiconductor apparatus, manufacturing method therefor, solid state image device and manufacturing method therefor  
An object of the present invention is to provide a semiconductor apparatus and a method of manufacturing the same, in which dispersion of a threshold voltage V th of a transistor at every...
6723593 Deep submicron MOS transistor with increased threshold voltage  
A deep submicron MOS transistor is formed with multiple control gates by forming side wall control gates adjacent to the gate oxide spacers over heavily-doped regions of the source and drain...
6720228 Current source bias circuit with hot carrier injection tracking  
A current mirror bias circuit for an RF amplifier transistor is modified whereby the reference transistor of the current mirror tracks hot carrier degradation in the RF transistor. Gate bias to the...
6720227 Method of forming source/drain regions in a semiconductor device  
A method of forming source/drain regions in a semiconductor device is provided. In one illustrative embodiment, the method comprises forming a gate electrode above a semiconducting substrate,...
6706605 Transistor formed from stacked disposable sidewall spacer  
A method of forming an integrated circuit transistor ( 80 ), comprising providing a semiconductor region ( 90 ) and forming a gate structure ( 92, 94 ) in a fixed position relative to the...
6677206 Non-volatile high-performance memory device and relative manufacturing process  
A non-volatile memory device including a plurality of memory cells, each memory cell formed as MOS transistor with a source region, a drain region and a gate having sides formed therewith; and one...
6660592 Fabricating a DMOS transistor  
Embodiment of the present invention are directed to improving the performance of a DMOS transistor. A method of fabricating a DMOS transistor comprises providing a semiconductor substrate having a...
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