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6465314 Semiconductor processing methods  
The invention pertains to semiconductor processing methods of implanting dopants into semiconductor substrates. In one aspect, the invention includes, a semiconductor processing method comprising:...
6465295 Method of fabricating a semiconductor device  
A semiconductor device fabrication method comprises the steps of forming a gate insulating film on a surface of a semiconductor substrate, forming a polysilicon film on the gate insulating film,...
6465311 Method of making a MOSFET structure having improved source/drain junction performance  
A MOSFET structure having substantially reduced parasitic junction capacitance, relaxed thermal budget constraints and resiliency to hot carrier damage is disclosed. The MOSFET structure includes a...
6465312 CMOS transistor with amorphous silicon elevated source-drain structure and method of fabrication  
A method of fabricating CMOS transistors having an elevated source-drain structure. The method utilizes the formation of L-shaped spacers on the gate stack followed by amorphous silicon (a-Si)...
6465332 Method of making MOS transistor with high doping gradient under the gate  
The invention is directed to a method of manufacturing an area of a first type of conductivity extending a depth into a semiconductor substrate and having a doping gradient as a function of the...
6461923 Sidewall spacer etch process for improved silicide formation  
Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein silicon substrate surfaces...
6461928 Methodology for high-performance, high reliability input/output devices and analog-compatible input/output and core devices using core device implants  
A method for fabricating an integrated circuit having analog and digital core devices. Using a first masking layer ( 118 ), a p-type type dopant is implanted to form drain extension regions ( 126,...
6461922 METHOD FOR THE INTEGRATION OF RESISTORS AND ESD SELF-PROTECTED TRANSISTORS IN AN INTEGRATED DEVICE WITH A MEMORY MATRIX MANUFACTURED BY MEANS OF A PROCESS FEATURING SELF-ALIGNED SOURCE (SAS) FORMATION AND JUNCTION SALICIDATION  
A method of forming a doped region in an integrated circuit which includes a matrix of memory cells and lightly-doped drain transistors and which is fabricated by means of a process providing for a...
6461924 MOS transistor for high-speed and high-performance operation and manufacturing method thereof  
A MOS transistor of the present invention includes a semiconductor substrate of a first conductivity type impurity, a gate insulating layer formed on the semiconductor substrate, gate electrodes...
6458664 Method for fabricating a field-effect transistor having an anti-punch-through implantation region  
A simple method for fabricating a field-effect transistor having an anti-punch-through implantation region is provided. After the anti-punch-through implantation region is formed, a semiconductor...
6455389 Method for preventing a by-product ion moving from a spacer  
This invention relates to a method that prevents by-productions from moving from a spacer. In particular by using an offset liner, a liner with a treated surface and a spacer that is formed by...
6455383 Methods of fabricating scaled MOSFETs  
The scaled MOSFETs having a conductive barrier-metal layer sandwiched between a metal layer or a thick silicide layer on the top and a first conductive gate layer at the bottom are disclosed by the...
6451675 Semiconductor device having varied dopant density regions  
A method for fabricating a metal-oxide semiconductor (MOS) transistor. A substrate having a gate structure is provided. The method of the invention includes forming a liner spacer on each side of...
6448167 Process flow to reduce spacer undercut phenomena  
A process for forming a composite insulator spacer on the sides of a MOSFET gate structure, wherein the underlying component of the composite insulator spacer is comprised of a thin silicon oxide...
6448142 Method for fabricating a metal oxide semiconductor transistor  
A fabrication method for a metal oxide semiconductor transistor is described. A source/drain implantation is conducted on a substrate beside the spacer that is on the sidewall of the gate to form a...
6444531 Disposable spacer technology for device tailoring  
The present provides a method for tailoring silicon dioxide source and drain implants and, if desired, extension implants of different devices used on a semiconductor wafer in order to realize...
6440809 Method of preventing fluorine ions from residing in a gate to result in boron ion penetration into a gate oxide  
The present invention provides a method of preventing fluorine ions from residing in a gate to result in boron ion penetration into a gate oxide on a semiconductor wafer. A substrate, an oxide...
6440808 Damascene-gate process for the fabrication of MOSFET devices with minimum poly-gate depletion, silicided source and drain junctions, and low sheet resistance gate-poly  
A sub-0.1 μm MOSFET device having minimum poly depletion, salicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene-gate process wherein the...
6441433 Method of making a multi-thickness silicide SOI device  
A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions...
6436778 Re-oxidation approach to improve peripheral gate oxide integrity in a tunnel nitride oxidation process  
A process for fabricating a semiconductor device 20 that includes providing semiconductor substrate 28 having a core region 24 and a peripheral gate region 26 . The semiconductor substrate ...
6436777 Semiconductor device and manufacturing method thereof  
An object is to provide a semiconductor device having an insulated-gate transistor which operates at high speed with low power consumption and a manufacturing method thereof. Two source/drain...
6436776 Process for fabricating a aligned LDD transistor  
A shallow impurity diffusion layer adjacent to a gate electrode is formed by forming a side-wall insulating film of the gate electrode twice, and a MOS transistor of the salicide type having...
6432785 Method for fabricating ultra short channel PMOSFET with buried source/drain junctions and self-aligned silicide  
The proposed method of the present invention forms MOSFETs with improved short channel effects and operating speeds over conventional devices. The method for fabricating MOSFETs includes the...
6432787 Method and apparatus for providing low-GIDL dual workfunction gate doping with borderless diffusion contact  
A semiconductor structure is provided along with a corresponding method of producing such a structure. The method and structure may include providing a semiconductor substrate, a gate insulator...
6432786 Method of forming a gate oxide layer with an improved ability to resist the process damage  
A method of forming a gate oxide layer with improved ability to resist process damage increases the reliability and yield of a transistor device. First, a nitrogen-containing gate oxide layer is...
6429083 Removable spacer technology using ion implantation to augment etch rate differences of spacer materials  
Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which has been treated subsequent to its...
6429084 MOS transistors with raised sources and drains  
In raised source/drain CMOS processing, the prior art problem of lateral epi growth on the gate stack interfering physically with the raised S/D structures and producing device characteristics that...
6429062 Integrated-circuit manufacturing using high interstitial-recombination-rate blocking layer for source/drain extension implant  
In the fabrication of a 0.10 micron CMOS integrated circuit, a high-energy plasma etch is used to pattern a polysilicon layer and an underlying gate oxide layer to define gate structures. A thermal...
6426524 Fabricating a square spacer  
A square spacer and method of fabrication. The method includes forming a spacer film on a mandrel positioned on a substrate, forming an oxide film on the spacer film, performing a first etching,...
6420236 Hydrogen treatment for threshold voltage shift of metal gate MOSFET devices  
A system for producing metal gate MOSFETs having relatively low threshold voltages is disclosed, comprising the steps of forming 200 a gate oxide layer on a semiconductor substrate, forming 210 ...
6420767 Capacitively coupled DTMOS on SOI  
A transistor structure is provided comprising a source region having a N + source region and a N − lightly doped source region. The structure also comprises a drain region having a N + drain...
6417056 Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge  
A method for forming a transistor having low overlap capacitance by forming a microtrench at the gate edge to reduce effective dielectric constant is described. A gate electrode is provided...
6417046 Modified nitride spacer for solving charge retention issue in floating gate memory cell  
A modified nitride spacer and making of the same are disclosed. The modified nitride spacer is formed adjacent a high-temperature oxide (HTO) layer which in turn is formed adjacent the sidewalls of...
6413811 Method of forming a shared contact in a semiconductor device including MOSFETS  
An objective of this invention is to provide a process for manufacturing a shared contact without protrusion toward an adjacent gate electrode and an improved shared contact. This invention allows...
6413808 Semiconductor device and process for production thereof  
In the semiconductor device disclosed in the present invention, the well regions in the internal circuit comprise high-impurity-concentration regions 4 and 5 as lower layers and...
6413810 Fabrication method of a dual-gate CMOSFET  
A fabrication method for fabricating a dual-gate CMOSFET on a semiconductor substrate according to the present invention includes: implanting ions of N-type impurity for forming a deep junction...
6410382 Fabrication method of semiconductor device  
A fabrication method of a semiconductor device improves the hot carrier immunity and prevents the deterioration of electrical characteristics of p-channel transistors. The fabrication method of the...
6410392 Method of producing MOS transistor  
The surface of a silicon substrate is sputter-etched so that silicon clusters sputtered out form a silicon film on a side wall spacer. Then, a metal film of cobalt, titanium or the like is built up...
6407436 Semiconductor device with abrupt source/drain extensions with controllable gate electrode overlap  
A method for forming source/drain extensions with gate overlap. An oxide layer is formed on a semiconductor substrate and a gate structure on the semiconductor substrate. First, sidewall spacer...
6406950 Definition of small damascene metal gates using reverse through approach  
Various methods of fabricating circuit devices incorporating a gate stack are disclosed. In one aspect, a method of fabricating a circuit device on a substrate is provided that includes forming a...
6406964 Method of controlling junction recesses in a semiconductor device  
The present invention is directed to a method of forming a transistor. In one embodiment, the method comprises providing a substrate, the substrate being doped with a first type of dopant material,...
6406951 Fabrication of fully depleted field effect transistor with raised source and drain in SOI technology  
For fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, an insulating block comprised of insulating material is formed on a thin...
6403432 Hardmask for a salicide gate process with trench isolation  
A method for forming of a self-aligned polysilicon gate MOSFET with silicon oxide shallow trench isolation is described wherein a hardmask is used to etch the polysilicon gate electrode. The...
6399453 Process of manufacturing semiconductor integrated circuit device having an amorphous silicon gate  
Desired operating characteristics are obtained from an MISFET in which a p-type silicon gate electrode is used by preventing the leakage of boron into the channel region in the following way....
6399451 Semiconductor device having gate spacer containing conductive layer and manufacturing method therefor  
A semiconductor device with a gate spacer containing a conductive layer, and a manufacturing method. A first spacer insulation layer is formed on a semiconductor substrate where a gate electrode is...
6399452 Method of fabricating transistors with low thermal budget  
A low thermal budget transistor is fabricated by first forming a gate on a semiconductor substrate. First amorphous regions and first inactive dopant regions are then created in the substrate by...
6399432 Process to control poly silicon profiles in a dual doped poly silicon process  
For use with sub-micron CMOS technologies, a gate etch process improves control of the etch profile. Gate stacks utilize N-type or P-type doped amorphous or poly silicon to enhance device...
6395624 Method for forming implants in semiconductor fabrication  
The present invention provides a novel method of forming implants with Projection Gas-Immersion Laser Doping (PGILD) process that overcomes the disadvantages of the prior art methods. In...
6395606 MOSFET with metal in gate for reduced gate resistance  
A MOS semiconductor device is formed with reduced parasitic junction capacitance and reduced gate resistance. Embodiments include forming oxide sidewall spacers on side surfaces of openings in a...
6391733 Method of doping semiconductor devices through a layer of dielectric material  
A method of making a semiconductor device includes performing a doping implant through a layer of dielectric material. The implanting through dielectric material enables use of high-energy implants...
Matches 401 - 450 out of 1334 < 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 >