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7101764 High-voltage transistor and fabrication process  
A high-voltage transistor and fabrication process in which the fabrication of the high-voltage transistor can be readily integrated into a conventional CMOS fabrication process. The high-voltage...
7098111 Manufacturing method of semiconductor integrated circuit device  
A manufacturing technology of a MOSFET having a shallow junction and a source and drain of a low resistance is provided. After having ion-implanted an As on the surface of a p type well forming a...
7094642 Method of fabricating semiconductor device  
An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region ( 3 ), and one...
7094652 Semiconductor device and method of manufacturing the same  
Disclosed is a semiconductor device comprising a first transistor and a second transistor formed on a semiconductor substrate, wherein a gate side wall of the second transistor has a thickness...
7094654 Manufacture of electronic devices comprising thin-film transistors  
A method of manufacturing an electronic device including a thin film transistor comprises forming a semiconductor film over an insulating substrate; depositing a first masking layer over the...
7091098 Semiconductor device with spacer having batch and non-batch layers  
A semiconductor device including a gate stack located over a substrate and a spacer located over the substrate and adjacent the gate stack. The spacer includes a plurality of layers, wherein at...
7091097 End-of-range defect minimization in semiconductor device  
A method of fabricating a semiconductor device comprises forming a gate electrode over a substrate and forming deep amorphous regions within the substrate. And implanting dopants to form deep...
7084039 Method of fabricating MOS transistor  
A method of fabricating a CMOS (complementary metal oxide semiconductor) transistor includes manufacturing steps, by which adverse transistor characteristics can be prevented from being degraded by...
7081393 Reduced dielectric constant spacer materials integration for high speed logic gates  
An FET transistor has a gate disposed between a source and a drain; a gate dielectric layer disposed underneath the gate; and a spacer on a side of the gate. The gate dielectric layer is...
7078303 Method for manufacturing semiconductor device having thick insulating layer under gate side walls  
A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall...
7074684 Elevated source drain disposable spacer CMOS  
In one embodiment of the invention, source and drain regions are formed as well as source and drain contact regions. Thereafter source and drain extension regions are formed. In another embodiment,...
7074665 Method of fabricating semiconductor device  
An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region ( 3 ), and one...
7071068 Transistor and method for fabricating the same  
A transistor and a method for fabricating the same that involves a forming a device isolation oxide film semiconductor substrate, forming an opening in the device isolation oxide to open the...
7060580 Field effect transistor and method of fabricating the same  
Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming...
7056799 Method of forming wing gate transistor for integrated circuits  
A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion...
7052965 Methods of fabricating MOS field effect transistors with pocket regions using implant blocking patterns  
MOSFETs with pocket regions are fabricated. A gate electrode layer is formed on a semiconductor substrate; and lightly doped drain regions are formed in the semiconductor substrate adjacent the...
7045433 Tip architecture with SPE for buffer and deep source/drain regions  
A method of manufacturing a semiconductor device includes forming a gate, source/drain extensions, buffer regions, and source/drain regions. The gate is formed over a semiconductor layer, and the...
7037796 Method of manufacturing spacers on sidewalls of titanium polycide gate  
Disclosed is a method for manufacturing a semiconductor device, more particularly to a method of forming a spacer on side-walls of a titanium polycide gate. The method for manufacturing the...
7038258 Semiconductor device having a localized halo implant therein and method of manufacture therefor  
The present invention provides a semiconductor device 200 having a localized halo implant 250 located therein, a method of manufacture therefore and an integrated circuit including the...
7033895 Method of fabricating a MOS transistor with elevated source/drain structure using a selective epitaxial growth process  
In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective...
7022565 Method of fabricating a trench capacitor of a mixed mode integrated circuit  
A method of fabricating a trench capacitor of a mixed mode integrated circuit includes forming shallow trench isolation regions for isolating active/passive devices on a semiconductor substrate....
7022577 Method of forming ultra shallow junctions  
The present invention relates to a method of fabricating a semiconductor device. In specific embodiments, the method comprises providing a semiconductor substrate, and ion implanting dopant...
7022596 Method for forming rectangular-shaped spacers for semiconductor devices  
A semiconductor device and method of making the same forms a spacer by depositing a spacer layer over a substrate and a gate electrode and forms a protective layer on the spacer layer. The...
7015095 Method for fabricating a semiconductor memory having charge trapping memory cells and semiconductor substrate  
Electrically conductive material is introduced into interspaces between the word lines ( 2 ) and is partially removed using a mask ( 6 ) in such a way that residual portions ( 7 ) of the conductive...
7015108 Implanting carbon to form P-type drain extensions  
The use of a carbon implant, in addition to the conventional fluorine implant, may significantly reduce the transient enhanced diffusion in P-type source drain extension regions. As a result,...
7015107 Method of manufacturing semiconductor device  
When a dummy sidewall and source and drain regions are once formed and then the dummy sidewall is removed to extend the source and drain regions, the removal of the dummy sidewall is performed...
7012008 Dual spacer process for non-volatile memory devices  
In a two-step spacer fabrication process for a non-volatile memory device, a thin oxide layer is deposited on a wafer substrate leaving a gap in the core of the non-volatile memory device....
7001818 MIS semiconductor device and manufacturing method thereof  
By suppressing a short-channel effect of a MIS field-effect transistor and reducing a fringing capacitance of a gate, a signal delay in the transistor can be shortened. The MIS field-effect...
7001817 Method for fabricating a semiconductor device  
A method for fabricating a semiconductor device, including forming a gate insulating film and a gate electrode film on a semiconductor substrate, and patterning the gate electrode film to form a...
6995052 Method and structure for double dose gate in a JFET  
A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant...
6987049 Semiconductor transistors and methods of fabricating the same  
In an example method for fabricating a transistor in a semiconductor device, a buffer insulation layer and a first insulation layer are deposited and etched, and poly electrodes for an LDD are...
6984566 Damascene gate process  
The invention provides a damascene gate process. A semiconductor substrate having a pad layer and an etch stop layer formed thereon is provided, and an insulating layer is formed to cover the etch...
6982229 Ion recoil implantation and enhanced carrier mobility in CMOS device  
An integrated circuit (IC) includes a CMOS device formed above a semiconductor substrate having ions therein that are implanted in the semiconductor substrate by an ion recoil procedure. The IC...
6969646 Method of activating polysilicon gate structure dopants after offset spacer deposition  
A process sequence used to integrate an anneal cycle, used to activate ion implanted dopants in a polysilicon gate structure, and the definition of offset silicon oxide spacers on the sides of the...
6962853 Semiconductor device and method for fabricating the same  
A conductive film for gate electrode including a polysilicon film is deposited on a semiconductor substrate, and patterned to form gate electrodes. An oxide film is formed on each side face of at...
6960512 Method for manufacturing a semiconductor device having an improved disposable spacer  
The present invention provides methods for manufacturing semiconductor devices. In one embodiment, the method includes forming a gate oxide over a substrate and a gate electrode over the gate...
6956276 Semiconductor device with an L-shaped/reversed L-shaped gate side-wall insulating film  
Provided is a semiconductor device, comprising a gate electrode formed on a semiconductor substrate, source/drain diffusion layers formed on both sides of the gate electrode, a gate electrode...
6955997 Laser thermal annealing method for forming semiconductor low-k dielectric layer  
A method of manufacturing a semiconductor device, including depositing a first layer of dielectric material onto the device, laser thermal annealing a surface of the first layer, and depositing a...
6953732 Method of manufacturing a semiconductor device including a mosfet with nitride sidewalls  
A method of manufacturing a semiconductor device includes providing a semiconductor substrate, and then forming a gate insulating layer on the semiconductor substrate. A lower gate electrode layer...
6946352 CMOS image sensor device and method  
A photodiode device including a well located in a substrate, a floating node located in the well and shallow trench isolation (STI) regions located over and laterally opposing the floating node. A...
6943082 Method for manufacturing a nonvolatile memory device  
A method, for manufacturing a nonvolatile memory device, includes: forming a gate layer above which a stopper layer is disposed on a semiconductor layer; forming control gates on both side surfaces...
6940137 Semiconductor device having an angled compensation implant and method of manufacture therefor  
The present invention provides a semiconductor device 200 having an angled compensation implant, a method of manufacture therefore and a method of manufacturing an integrated circuit including...
6924237 Method for manufacturing semiconductor integrated circuit device  
A method is used to form a circuit to achieve a high-speed performance and a circuit to attain a high reliability on one and the same substrate, in a semiconductor integrated circuit device...
6924200 Methods using disposable and permanent films for diffusion and implantation doping  
Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and...
6913980 Process method of source drain spacer engineering to improve transistor capacitance  
A method of forming an associated transistor is presented whereby short channel effects and junction capacitances are mitigated and enhanced switching speeds are thereby facilitated. Compensation...
6908822 Semiconductor device having an insulating layer and method for forming  
An insulating layer ( 24, 66, 82 ) is formed over a stack ( 14 ) of materials and a semiconductor substrate ( 12 ) and an implant is performed through the insulating layer into the semiconductor...
6908839 Method of producing an imaging device  
The invention relates to a dual masked spacer etch for improved dark current performance in imagers. After deposition of spacer material such as oxide, N-channel regions are first opened for N + ...
6908833 Shallow self isolated doped implanted silicon process  
A process and structure for forming electrical devices. The process and structure provide for forming an insulating layer on a substrate. A conductive region is then formed in the insulating layer...
6905922 Dual fully-silicided gate MOSFETs  
A semiconductor device having a plurality of silicidation steps is provided. In the preferred embodiment in which the semiconductor device is a MOSFET, the source/drain regions are silicided. A...
6905923 Offset spacer process for forming N-type transistors  
A method of fabricating an SMOS integrated circuit with source and drain junctions utilizes an offset gate spacer for N-type transistors. Ions are implanted to form the source and drain regions in...
Matches 151 - 200 out of 1334 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >