Matches 651 - 700 out of 1334 < 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 >
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6180477 Method of fabricating field effect transistor with silicide sidewall spacers  
A method of fabricating a field effect transistor is described. A gate oxide layer is formed on a substrate. A gate is formed on the gate oxide layer. A source region and a drain region are formed...
6180515 Method of fabricating self-align contact window with silicon nitride side wall  
A gate oxide layer, a polysilicon layer are patterned on a substrate. Then, a thermal oxidation is carried out to form the first silicon dioxide layer on the surface of the polysilicon layer. Then,...
6180471 Method of fabricating high voltage semiconductor device  
A method of fabricating a high voltage semiconductor device. A semiconductor substrate doped with a first type dopant and comprising a gate is provided. A cap oxide layer is formed on the gate...
6180476 Dual amorphization implant process for ultra-shallow drain and source extensions  
A method of fabricating an integrated circuit with ultra-shallow source/drain junctions which utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep...
6180443 Semiconductor device and method of fabricating the same  
A semiconductor device having a plurality of transistors connected in series in a semiconductor substrate, the device includes first and second gate electrodes on the semiconductor substrate, a...
6180468 Very low thermal budget channel implant process for semiconductors  
An ultra-low thermal budget process is provided for channel implant by using a reverse process sequence where a conventional MOS transistor is formed without the channel implant. The originally...
6180475 Transistor formation with local interconnect overetch immunity  
An integrated circuit transistor and a method for making the same are provided. The transistor is resistant to junction shorts due to the overetch of local interconnect trenches. The transistor...
6171917 Transistor sidewall spacers composed of silicon nitride CVD deposited from a high density plasma source  
A method is provided for forming high quality nitride sidewall spacers laterally adjacent to the opposed sidewall surfaces of a gate conductor dielectrically spaced above a semiconductor substrate....
6171919 MOS Transistor formation process including post-spacer etch surface treatment for improved silicide formation  
Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon...
6171915 Method of fabricating a MOS-type transistor  
To provide a method of fabricating a MOS-type transistor of a LDD structure with a gate electrode made of molybdenum, which brings about a reduction in the amount of overlapping between the gate...
6171916 Semiconductor device having buried gate electrode with silicide layer and manufacture method thereof  
A semiconductor device in which a salicide structure is applied to a buried gate transistor to largely reduce a difference of level or height in a element and to reduce the resistance of a gate...
6171918 Depleted poly mosfet structure and method  
A method for doping a poly depleted semiconductor transistor, the semiconductor transistor including a gate region, a source region adjacent the gate region and a drain region adjacent the gate...
6169006 Semiconductor device having grown oxide spacers and method of manufacture thereof  
A semiconductor device having grown oxide spacers and a method for manufacturing such a semiconductor device is provided. In one embodiment of the invention, a gate electrode is formed over a...
6165858 Enhanced silicidation formation for high speed MOS device by junction grading with dual implant dopant species  
A method of making a MOS transistors in an integrated circuit includes forming a plurality of doped source and drain regions adjacent respective gate structures that include gate dielectrics, gate...
6165913 Manufacturing method for spacer  
A method for manufacturing spacers comprising the steps of first providing a semiconductor substrate having a gate electrode already formed thereon, and then sequentially depositing oxide, silicon...
6165882 Polysilicon gate having a metal plug, for reduced gate resistance, within a trench extending into the polysilicon layer of the gate  
A device and method to reduce resistance in polysilicon gates by forming a highly conductive plug within a trench in the gate. This is achieved by etching a trench between nitride sidewalls and...
6165826 Transistor with low resistance tip and method of fabrication in a CMOS process  
A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the...
6165857 Method for forming a transistor with selective epitaxial growth film  
A new improvement for selective epitaxial growth is disclosed. In one embodiment, the present invention provides a low power metal oxide semiconductor field effect transistor (MOSFET), which...
6162710 Method for making MIS transistor  
Disclosed is a method for making a MIS transistor that a gate electrode and gate insulating film are formed on a semiconductor substrate with a channel region formed implanting an impurity of one...
6162716 Amorphous silicon gate with mismatched grain-boundary microstructure  
A method of forming an amorphous-Si (α-Si) gate with two or more α-Si layers with mismatched grains. The first embodiment involves forming two or more amorphous silicon layers over the gate...
6162694 Method of forming a metal gate electrode using replaced polysilicon structure  
A metal gate electrode formed with high temperature activation of source/drain and LDD implants and a process for manufacture. A polysilicon alignment structure is formed on a silicon substrate....
6162689 Multi-depth junction formation tailored to silicide formation  
High integrity ultra-shallow source/drain junctions are formed employing cobalt silicide contacts. Emdodiments include forming field oxide regions, gates, spacers, and lightly doped implants, and...
6159814 Spacer formation by poly stack dopant profile design  
A method for forming a semiconductor device to produce graded doping in the source region and the drain region includes the steps of implanting the gate material, usually a polysilicon, with a...
6159815 Method of producing a MOS transistor  
In order to produce a MOS transistor with HDD profile and LDD profile, the HDD profile is firstly formed, followed by the LDD profile, in the area for the LDD profile in order to produce steep...
6156615 Method for decreasing the contact resistance of silicide contacts by retrograde implantation of source/drain regions  
A semiconductor device and method of forming contacts for the semiconductor device performs a retrograde implant of dopant in the source/drain regions so that the concentration of the dopant within...
6156593 Method for fabricating salicide CMOS and non-salicide electrostatic discharge protection circuit in a single chip  
A method of fabricating an ESD protection circuit without salicide formation is described. First, isolation regions and gate structures are formed on a semiconductor substrate, then device regions...
6153485 Salicide formation on narrow poly lines by pulling back of spacer  
A method for a salicide process where S/D silicide contacts are formed in a separate silicide step than the gate silicide contacts. Preferably, TiSi 2 is formed on S/D regions and TiSi 2 or CoSi...
6146955 Method for forming dynamic random access memory device with an ultra-short channel and an ultra-shallow junction  
A Method for forming a dynamic random access memory device with an ultra-short channel and an ultra-shallow junction is described in the invention. In the invention, the spacer is used as a mask to...
6146954 Minimizing transistor size in integrated circuits  
A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal insulating space between polysilicon gate...
6146953 Fabrication method for mosfet device  
A fabrication method for a MOSFET device including the steps of forming a first insulating film on a semiconductor substrate wherein an active region and an isolated region are defined, forming a...
6143618 Procedure for elimating flourine degradation of WSi.sub.x /oxide/polysilicon capacitors  
A method for forming a polycide/oxide/polysilicon capacitor on a silicon wafer with improved dielectric stability and reliability is described wherein an in-situ high temperature anneal is applied...
6144068 Transistor device structures, and methods for forming such structures  
In one aspect, a method for forming a transistor device on a semiconductor substrate, comprising: a) forming a transistor gate on the substrate; b) forming a first polarity source active region and...
6140190 Method and structure for elevated source/drain with polished gate electrode insulated gate field effect transistors  
A method and structure are provided for an IGFET which has elevated source/drain regions and polished gate electrode. The IGFET provides raised doped polysilicon regions between the source/drain...
6140183 Method of fabricating semiconductor device  
A method of fabricating a semiconductor device an object of which is to form a semiconductor device having a DMOS with high withstanding pressure and high driving capacity and a highly precise...
6140216 Post etch silicide formation using dielectric etchback after global planarization  
The present invention describes the formation of a silicide layer upon a gate conductor by using a masking layer which covers the source/drain regions of the transistor. The method includes forming...
6140186 Method of forming asymmetrically doped source/drain regions  
Asymmetrically doped source/drain regions of a transistor are formed employing protective insulating layers to prevent a portion of the gate electrode from receiving an excessive impurity...
6136636 Method of manufacturing deep sub-micron CMOS transistors  
The present invention includes forming nitrogen-doped amorphous silicon layer on the gate structure and on a pad oxide. Nitride spacers are formed on the side walls of the gate structure. Then, the...
6136616 Method of forming semiconductor devices using gate electrode dimensions and dopant concentration for controlling drive current strength  
A semiconductor device having a controlled drive current strength is produced by varying dopant concentration to accommodate any variation in channel length, which is affected by variations in gate...
6136658 Method of fabricating a semiconductor device including a contact hole between gate electrode structures  
A method of fabricating a semiconductor device is provided which requires less distance allowance between gate electrodes and a contact hole, and which can therefore readily promote micro-fine...
6133101 Low mask count process to fabricate mask read only memory devices  
The present invention includes performing a blanket ion implantation to form lightly doped drain regions (LDD) adjacent to gate structures. A second ion implantation is performed with tilted angle...
6133104 Method of eliminating buried contact trench in MOSFET devices with self-aligned silicide including a silicon connection to the buried contact region which comprises a doped silicon sidewall  
The method of forming buried contacts on a semiconductor substrate is as follows. At first, a gate insulator layer is formed on the substrate. An undoped silicon layer is then formed on the...
6133122 Method of fabricating semiconductor device for preventing rising-up of siliside  
Disclosed is a manufacturing method of a semiconductor device which comprises which comprises an element isolation region formation step; a side wall formation step; a diffusion layer formation...
6130135 Method of fabricating lightly-doped drain transistor having inverse-T gate structure  
A method of fabricating a lightly doped drain transistor having an inverse-T gate structure. A semiconductor substrate is provided to implement said method. After a gate dielectric layer is formed...
6127234 Ultra shallow extension formation using disposable spacers  
The present invention is directed to a method of forming ultra shallow extensions in a transistor and a device incorporating same. The method comprises forming a gate dielectric and a gate...
6127216 Heavily-doped polysilicon/germanium thin film formed by laser annealing  
An ultra-large scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs utilize gate structures with...
6127235 Method for making asymmetrical gate oxide thickness in channel MOSFET region  
A semiconductor device has gate with a first material having a first dielectric constant adjacent the semiconductor substrate and a second material having a second dielectric constant adjacent the...
6124173 Method for improved storage node isolation  
A MOS gate and associated source/drain region structure providing three junction diodes between a source/drain contact area and the substrate, instead of the typical total of one, resulting in...
6124176 Method of producing a semiconductor device with reduced fringe capacitance and short channel effect  
A semiconductor device and a method of producing the same are disclosed. Cavities intervene between a gate electrode and a source and a drain region for reducing a capacitance. The cavities...
6124188 Semiconductor device and fabrication method using a germanium sacrificial gate electrode plug  
Semiconductor devices and fabrication processes which rely on the use of sacrificial gate electrode plugs are provided. In one embodiment, a germanium bearing plug is used to form a gate electrode....
6124190 Method of manufacturing semiconductor device with silicide layer without short circuit  
In a method of manufacturing a semiconductor integrated circuit, a gate structure with sidewall insulating films and a field oxidation film are formed on a semiconductor substrate. Then, diffusion...
Matches 651 - 700 out of 1334 < 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 >