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6339015 Method of fabricating a non-volatile semiconductor device  
A non-volatile random access memory (NVRAM) cell and methods of forming thereof are disclosed. The NVRAM cell includes a substrate having source and drain regions. A spike having a sharp tip...
6337249 Semiconductor device and fabrication process thereof  
A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a...
6337272 Method of manufacturing a semiconductor device  
A method of manufacturing a semiconductor device in which a cobalt silicide layer is formed on a semiconductor substrate. In the method, the semiconductor substrate is prepared, and cobalt is...
6335251 Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor  
A semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed is arranged to have a gate electrode which is formed on the surface of a silicon...
6335253 Method to form MOS transistors with shallow junctions using laser annealing  
A new method of forming MOS transistors with shallow source and drain extensions and self-aligned silicide in the has been achieved. Gates are provided overlying a semiconductor substrate....
6335252 Semiconductor device manufacturing method  
An MIS transistor manufacturing method which can prevent unwanted diffusion of extensions caused by the drive to the source/drain so that the diffusion of the source/drain and the diffusion of the...
6335254 Methods of forming transistors  
In accordance with an aspect of the invention, a transistor is formed having a transistor gate, a gate dielectric layer and source/drain regions. The transistor gate includes at least two...
6331458 Active region implant methodology using indium to enhance short channel performance of a surface channel PMOS device  
An MOS device is provided using indium as a threshold adjust implant in the channel regions of an NMOS device and/or in the conductive gate overlying the channel region in a PMOS device. Indium...
6329230 High-speed compound semiconductor device having an improved gate structure  
A semiconductor device includes a gate structure formed on a substrate in which an LDD structure is formed, wherein gate structure includes a Schottky electrode making a Schottky contact with a...
6329235 Method of performing a pocket implantation on a MOS transistor of a memory cell of a DRAM  
This invention provides a method of performing a pocket implantation on a MOS transistor of a memory cell of a DRAM. The DRAM on a predetermined area of a semiconductor wafer comprises memory cells...
6329252 Method of forming self-aligned contacts  
The invention advantageously provides a novel method for making self-aligned contacts on a semiconductor substrate. A gate electrode having a vertical sidewall and a protecting layer thereon is...
6326274 Method for improving performance and reliability of MOS technologies and data retention characteristics of flash memory cells  
A method of fabricating a semiconductor device wherein there is provided a semiconductor substrate, preferably of silicon, having a gate insulator thereover, preferably of silicon dioxide, forming...
6323095 Method for reducing junction capacitance using a halo implant photomask  
A method for forming a semiconductor device is provided. The method includes providing a substrate having a gate formed thereon. A first doped region is formed in the substrate. The first doped...
6323519 Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process  
A transistor and a method for making a transistor are described. A gate conductor is patterned over a gate dielectric upon a semiconductor substrate. Dopant impurity distributions self-aligned to...
6319807 Method for forming a semiconductor device by using reverse-offset spacer process  
A method for forming semiconductor devices is disclosed. The method of the present invention includes providing a semiconductor substrate, followed by forming shallow trench isolation (STI)...
6319785 Method for forming a contact in a semiconductor device  
A method for forming a contact is provides that can minimize junction leakage. In this method, A contact hole is opened in an insulating layer to expose an impurity diffusion layer in a...
6316322 Method for fabricating semiconductor device  
Submicron-dimensioned devices are formed whereby a desired relationship between the impurity concentration peak and a lightly doped source/drain region is obtained.
6316321 Method for forming MOSFET  
A method for forming MOSFET is disclosed. The method includes firstly providing a substrate, on which a gate without spacer is already formed. A first spacer is formed on sidewall of the gate, a...
6316323 Method for forming bridge free silicide by reverse spacer  
The proposed invention is used to prevent the bridging issue of salicide process and also to provide a self-aligned contacted process in conventional self-aligned silicide process. In short, the...
6316809 Analog MOSFET devices  
The specification describes MOS transistors for analog functions which have increased output impedance. The increased output impedance is the result of reduced drain depletion width. This is...
6316304 Method of forming spacers of multiple widths  
A method is described for forming gate sidewall spacers having different widths. The variation in spacer width allows for optimization of the MOSFET characteristics by changing the dimensions of...
6316319 Method of manufacturing a semiconductor device having shallow junctions  
A semiconductor device with shallow junctions is obtained by forming shallow source/drain extensions followed by forming a film over the gate electrode and the semiconductor substrate. The film is...
6312999 Method for forming PLDD structure with minimized lateral dopant diffusion  
A method for forming a MOSFET having an LDD structure with minimal lateral dopant diffusion is described. A gate electrode is provided overlying a gate dielectric layer on a semiconductor...
6309937 Method of making shallow junction semiconductor devices  
Disclosed is a technique to provide an integrated circuit substrate with a transistor gate member that has opposing sidewalls. A first spacer extends from one of the sidewalls and a second spacer...
6309936 Integrated formation of LDD and non-LDD semiconductor devices  
A method of forming a semiconductor device includes forming a first gate electrode over a substrate and then forming a spacer on at least one sidewall of the first gate electrode. A second gate...
6306715 Method to form smaller channel with CMOS device by isotropic etching of the gate materials  
A method to form a MOS transistor with a narrow channel regions and a wide top (second) gate portion. A gate dielectic layer and a first gate layer are formed over a substrate. A second gate...
6306701 Self-aligned contact process  
A self-aligned contact process. A substrate is provided. A gate including a polysilicon layer and a metal silicide layer is formed on the substrate. A cap layer is formed on the gate to protect the...
6303454 Process for a snap-back flash EEPROM cell  
The present invention provides method to fabricate a snap-back flash EEPROMS device. The method begins by forming a gate structure 22 24 28 26 on a substrate. The gate structure comprises: a tunnel...
6303450 CMOS device structures and method of making same  
Disclosed is a method comprising providing a silicon surface with an underlying insulator layer, providing a plurality of gates adjacent to source/drain regions, growing source/drains between the...
6303449 Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMP  
A method of manufacturing a self aligned elevated source/drain (S/D). A first insulating layer is formed over a substrate. The first insulating layer having at least a gate opening and source/drain...
6303452 Method for making transistor spacer etch pinpoint structure  
A method is provided for forming a transistor spacer etch endpoint structure of an integrated circuit, and an integrated circuit formed according to the same. A gate is formed over a portion of a...
6300207 Depleted sidewall-poly LDD transistor  
The present invention is directed to a metal oxide semiconductor transistor having a fully overlapped lightly doped drain (LDD) structure which offers the advantages of conventional fully...
6300656 Nonvolatile semiconductor memory device having a drain region of different impurity density and conductivity types  
A nonvolatile semiconductor memory device includes an n-type region which is in contact with n + drain diffusion region at a surface of p-type silicon substrate and covers the periphery thereof....
6300205 Method of making a semiconductor device with self-aligned active, lightly-doped drain, and halo regions  
One method of making a semiconductor device includes forming a gate electrode on a substrate and forming a spacer on a sidewall of the gate electrode. An active region is then formed in the...
6297114 Semiconductor device and process and apparatus of fabricating the same  
A semiconductor device having a gate electrode on a Si-substrate through a gate oxide film; a first impurity diffusion region having a conductivity type reversed to a well which will form a part of...
6297104 Methods to produce asymmetric MOSFET devices  
Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are disclosed. One MOSFET includes, a substrate having a well of a first conductivity type. The MOSFET also includes source and drain...
6297117 Formation of confined halo regions in field effect transistor  
Halo regions are formed for a field effect transistor having a gate structure on a gate dielectric within an active device area of a semiconductor substrate. A first dummy spacer is formed on a...
6297116 Method for manufacturing a metal oxide semiconductor (MOS)-based structure  
A method for manufacturing a metal oxide semiconductor (MOS)-based structure is provided. The method includes the steps of (a) providing a substrate, (b)forming a conducting layer on a portion of...
6297115 Cmos processs with low thermal budget  
A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual-amorphization technique. The technique creates a shallow amorphous region and a deep...
6294415 Method of fabricating a MOS transistor  
An improved method of fabricating a MOS transistor on a semiconductor wafer is disclosed. A pre-amorphization implant (PAI) process is used to dope the silicon substrate adjacent to the gate. The...
6294432 Super halo implant combined with offset spacer process  
A method for forming a semiconductor structure by using super halo implant combined with offset spacer process is disclosed. This invention comprises providing a substrate with a gate electrode...
6294435 Method of reducing word line resistance and contact resistance  
By introducing a carefully controlled anneal step after the deposition of tungsten silicide (onto a layer of polysilicon) but before the deposition of a layer of silicon oxide, interaction between...
6291302 Selective laser anneal process using highly reflective aluminum mask  
A method of providing a field effect transistor includes depositing a layer of a laser-reflective material on a substrate which has an active region and an inactive region; selectively removing...
6291329 Protective oxide buffer layer for ARC removal  
An oxide buffer layer is formed between an underlying silicon layer and overlying ARC to prevent damage to the silicon layer when removing the ARC. Embodiments include depositing a silicon oxide...
6291354 Method of fabricating a semiconductive device  
A method of fabricating a semiconductor device is described in which an insulation layer is formed over the gate electrode and the substrate. This insulation layer is anisotropically etched away...
6291278 Method of forming transistors with self aligned damascene gate contact  
A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the...
6287925 Formation of highly conductive junctions by rapid thermal anneal and laser thermal process  
For forming a highly conductive junction in an active device area of a semiconductor substrate, a first dopant is implanted into the active device area to form a preamorphization region. A second...
6287877 Electrically quantifying transistor spacer width  
A method for electrically quantifying a semiconductor device's spacers' width. In one embodiment, a method comprises the step of measuring a resistance across a region of interest of each of a...
6284607 Method of making high-voltage HV transistors with drain extension in a CMOS process of the dual gate type with silicide  
In a CMOS process for making dual gate transistors with silicide, high-voltage transistors with drain extensions are produced by first defining on a semiconductor substrate, active areas for...
6284612 Process to fabricate ultra-short channel MOSFETs with self-aligned silicide contact  
The method of the present invention includes the following steps. First, a gate oxide layer is formed on the substrate. An undoped polysilicon layer is formed over the gate oxide layer. Then, a...
Matches 501 - 550 out of 1338 < 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 >