Matches 451 - 500 out of 1334 < 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 >
Match Document Document Title
6391752 Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane  
A method of fabricating a SOI semiconductor device with an implanted ground plane in the silicon substrate to increase the doping concentration underneath the channel region for suppressing...
6391730 Process for fabricating shallow pocket regions in a non-volatile semiconductor device  
A process for fabricating shallow pocket regions in a non-volatile semiconductor device includes providing a semiconductor substrate having a principal surface. A masking pattern is formed to...
6391728 Method of forming a highly localized halo profile to prevent punch-through  
The disclosure describes an exemplary embodiment relating to a method of forming halo regions in an integrated circuit. This method includes forming dummy spacer structures over an integrated...
6391731 Activating source and drain junctions and extensions using a single laser anneal  
A new method of forming MOS transistors with shallow source and drain extensions and deep source and drain junctions in the manufacture of an integrated circuit device has been achieved. Gates are...
6391732 Method to form self-aligned, L-shaped sidewall spacers  
A new method of forming silicon nitride sidewall spacers has been achieved. In addition, a new device profile for a silicon nitride sidewall spacer has been achieved. An isolation region is...
6387767 Nitrogen-rich silicon nitride sidewall spacer deposition  
Salicide processing is implemented with nitrogen-rich silicon nitride sidewall spacers that allow a metal silicide layer e.g., NiSi, to be formed over the polysilicon gate electrode and...
6383883 Method of reducing junction capacitance of source/drain region  
A method of reducing junction capacitance of a source/drain region. A gate oxide layer is formed on a first conductive type substrate. A polysilicon layer is formed and patterned on the gate. Light...
6383906 Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption  
A method for forming ultra shallow junctions in a semiconductor wafer uses disposable spacers and a silicon cap layer to achieve ultra-low low silicon consumption during a salicide formation...
6383917 Method for making integrated circuits  
An improved method for making an integrated circuit. That method includes forming a first dielectric layer on a substrate, etching a trench into that layer, then filling the trench with a...
6380041 Semiconductor with laterally non-uniform channel doping profile and manufacturing method therefor  
An ultra-large scale integrated circuit semiconductor device having a laterally non-uniform channel doping profile is manufactured by using a Group IV element implant at an implant angle of between...
6380053 Method for producing a semiconductor device with an accurately controlled impurity concentration profile in the extension regions  
A method for producing a semiconductor device comprising the steps of: (A) forming a gate insulating layer on a surface of a semi-conductive layer, and then, forming a gate electrode on a gate...
6380043 Low temperature process to form elevated drain and source of a field effect transistor having high-K gate dielectric  
For fabricating a field effect transistor, a gate structure is formed on a gate dielectric on an active device area of a semiconductor substrate. An amorphization dopant and an extension dopant are...
6380038 Transistor with electrically induced source/drain extensions  
A method of fabricating an integrated circuit provides a transistor having less susceptibility to short channel effects. The transistor utilizes a U-shaped gate conductor and a main gate conductor....
6376321 Method of making a pn-junction in a semiconductor element  
A pn-junction in a semiconductor element is made in that, within a zone of a first conductivity type, by means of implantation, a first and second zone of a second conductivity type are formed...
6372585 Semiconductor device method  
This invention is to a method for producing a uniform nitrogen doped layer in silicon that effectively reduces boron transient enhanced diffusion (TED) for ultra shallow junction formation. A...
6372590 Method for making transistor having reduced series resistance  
A transistor having reduced series resistance and method for producing the same. The method reduces transistor series resistance by implanting nitrogen into an nLDD/Source/Drain extension region of...
6372591 Fabrication method of semiconductor device using ion implantation  
A fabrication method of a semiconductor device is provided, which makes it possible to form shallow extensions (e.g., 0.1 μm or less in depth) of source/drain regions of a MOSFET with a double...
6368922 Internal ESD protection structure with contact diffusion  
An ESD protected structure and method of its fabrication are disclosed. A heavily doped polycrystalline silicon region of a first conductivity type is disposed on a substrate surface and is...
6368926 Method of forming a semiconductor device with source/drain regions having a deep vertical junction  
The present invention is directed to a method of forming source/drain regions in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate stack above a...
6365472 Semiconductor device and method of manufacturing the same  
A semiconductor device comprises an LDD structure MOS transistor wherein the formation of defects due to ion implantation at the edge of the side wall of the gate electrode is suppressed. In order...
6365474 Method of fabricating an integrated circuit  
A transistor ( 12 ) and method of making an integrated circuit ( 10 ) uses a chromium based sacrificial gate ( 22 A) to align, dope and activate source and drain portions ( 36, 38, 52, 53, ) of the...
6365463 Method for forming a high-precision analog transistor with a low threshold voltage roll-up and a digital transistor with a high threshold voltage roll-up  
A process for forming high-precision analog transistors with a low threshold voltage roll-up and digital transistors with a high threshold voltage roll-up is disclosed. The process selectively...
6365464 Method to eliminate shorts between adjacent contacts due to interlevel dielectric voids  
A method to form contacts in an integrated circuit device comprising to eliminate shorting between adjacent contacts due to dielectric layer voids is achieved. A substrate is provided. Narrowly...
6365496 Elimination of junction spiking using soft sputter etch and two step tin film during the contact barrier deposition process  
A contact opening to a silicon substrate within which a metal contact is to be formed is cleaned by soft sputter etch to clean the substrate surface and remove any residue which would interfere...
6365476 Laser thermal process for fabricating field-effect transistors  
A simplified and cost reduced process for fabricating a field-effect transistor semiconductor device ( 104 ) using laser radiation is disclosed. The process includes the step of forming removable...
6362058 Method for controlling an implant profile in the channel of a transistor  
A method of fabricating an integrated circuit ( 10, 51, 61, 71, 81, 91 ) includes forming on the upper surface ( 13 ) of a substrate ( 12 ) a part ( 18 ) which has thereon a side surface ( 19 ). A...
6362060 Method for forming semiconductor device having a gate in the trench  
A trench or a recess is formed in a predetermined part of a semiconductor substrate. Then, on the side of the trench or recess, a gate with a sidewall is formed by respective etching-back...
6362117 Method of making integrated circuit with closely spaced components  
An integrated circuit ( 10, 60, 110, 210 ) is fabricated according to a method which includes the steps of providing a structure ( 12, 112, 212 ) having a top surface ( 13, 113, 213 ), and forming...
6358802 Method for manufacturing semiconductor device having a gate electrode film containing nitrogen  
There is disclosed a semiconductor device which includes a semiconductor substrate having an element region and source and drain regions, a gate dielectric film containing nitrogen formed in the...
6358805 Method of making a SOI device having fixed channel threshold voltage  
In a semiconductor device and method for manufacturing the same, a buried insulating layer is formed on a semiconductor substrate, multiple depletion regions of a first conductivity type are formed...
6358787 Method of forming CMOS integrated circuitry  
A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate...
6358803 Method of fabricating a deep source/drain  
Methods of fabricating source/drain regions and transistors incorporating the same are provided. In one aspect, a method of fabricating a source/drain region in a substrate is provided that...
6352900 Controlled oxide growth over polysilicon gates for improved transistor characteristics  
A method for controlled oxide growth on transistor gates. A first film ( 40 ) is formed on a semiconductor substrate ( 10 ). The film is implanted with a first species and patterned to form a...
6350637 Method of fabrication of a no-field MOS transistor  
Method of fabrication of a no-field transistor with no extra process costs, providing for defining an active area for the transistor surrounded by a thick field oxide layer, insulatively placing a...
6350127 Method of manufacturing for CMOS image sensor  
A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provide, containing p-type and/or n-type regions which are bounded by isolation regions and with gate...
6350641 Method of increasing the depth of lightly doping in a high voltage device  
A method for fabricating a high vltage device with double diffusion structure provides a pad oxide layer on a silicon substrate. A silicon nitride layer is formed and patterned to expose isolation...
6350696 Spacer etch method for semiconductor device  
Spacers are formed on a semiconductor device by depositing a spacer layer on the semiconductor device. The semiconductor device is subjected to an anisotropic etching process to leave at least a...
6348389 Method of forming and etching a resist protect oxide layer including end-point etch  
The present invention provides a method for forming and etching a resist protect oxide layer, of which provides improved etch selectivity to a shallow trench isolation and an increased pre-metal...
6346450 Process for manufacturing MIS transistor with self-aligned metal grid  
This invention relates to a MIS transistor and its manufacturing process. The process comprises the following steps: a) production of a dummy grid on a substrate, made of a material capable of...
6346439 Semiconductor transistor devices and methods for forming semiconductor transistor devices  
The invention includes a method for forming graded junction regions comprising: a) providing a semiconductor material wafer; b) providing a transistor gate over the semiconductor material wafer,...
6346449 Non-distort spacer profile during subsequent processing  
A method for fabricating a junction for a field effect transistor which does not cause distortion of the sidewall spacers during subsequent processing thereby reducing junction depletion and source...
6344398 Method for forming transistor devices with different spacer width  
A method for forming transistor devices with different spacer width for mixed-mode IC is provided. The method provides three different kinds of transistor devices on a wafer, two of them have their...
6344397 Semiconductor device having a gate electrode with enhanced electrical characteristics  
In one illustrative embodiment, the present invention is directed to forming a masking layer ( 104 ) above a semiconducting substrate ( 102 ), forming an opening ( 105 ) in the masking layer ( 104...
6342423 MOS-type transistor processing utilizing UV-nitride removable spacer and HF etch  
Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its...
6342422 Method for forming MOSFET with an elevated source/drain  
A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. A first dielectric layer is formed over the first silicon...
6340617 Manufacture of semiconductor device  
A method of manufacturing a semiconductor device having shallow p-n junctions and silicide regions, capable of meeting both requirements of a high annealing temperature and a low annealing...
6339015 Method of fabricating a non-volatile semiconductor device  
A non-volatile random access memory (NVRAM) cell and methods of forming thereof are disclosed. The NVRAM cell includes a substrate having source and drain regions. A spike having a sharp tip...
6337249 Semiconductor device and fabrication process thereof  
A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a...
6337272 Method of manufacturing a semiconductor device  
A method of manufacturing a semiconductor device in which a cobalt silicide layer is formed on a semiconductor substrate. In the method, the semiconductor substrate is prepared, and cobalt is...
6335251 Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor  
A semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed is arranged to have a gate electrode which is formed on the surface of a silicon...
Matches 451 - 500 out of 1334 < 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 >