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8182710 Structuring method  
A method of structuring multicrystalline silicon surfaces comprises the provision of a texturing solution, the application of the texturing solution to a surface of a semiconductor substrate to be...
8183106 Apparatus and associated method for making a floating gate memory device with buried diffusion dielectric structures and increased gate coupling ratio  
A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional...
8168488 Systems and methods for reducing contact to gate shorts  
A method for reducing contact to gate shorts in a semiconductor device and the resulting semiconductor device are described. In one embodiment, a gate is formed on a substrate, a contact is formed...
8148227 Method for providing a self-aligned conductive structure  
An embodiment according to the present invention comprises a method for providing a self-aligned conductive structure comprising providing a first structure on a surface, wherein the first...
8143131 Method of fabricating spacers in a strained semiconductor device  
The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack,...
8143670 Self aligned field effect transistor structure  
Provided is a self aligned filed effect transistor structure. The self aligned field effect transistor structure includes: an active region on a substrate; a U-shaped gate insulation pattern on the...
8138052 Metal high dielectric constant transistor with reverse-T gate  
A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain...
8138055 Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same  
In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate...
8134152 CMOS thin film transistor, method of fabricating the same and organic light emitting display device having laminated PMOS poly-silicon thin film transistor with a top gate configuration and a NMOS oxide thin film transistor with an inverted staggered bottom gate configuration  
A CMOS thin film transistor arrangement including a PMOS poly-silicon thin film transistor having a top gate configuration and a NMOS oxide thin film transistor having an inverted staggered bottom...
8129247 Omega shaped nanowire field effect transistors  
A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire on a semiconductor substrate, forming a first gate structure on a first portion of the nanowire,...
8129235 Method of fabricating two-step self-aligned contact  
A method of fabricating a self-aligned contact is provided. A first dielectric layer is formed on a substrate having a contact region therein. Next, a lower hole corresponding to the contact region...
8124512 Methods of forming integrated circuit devices having different gate electrode cross sections  
A semiconductor device includes a first conductive structure and a second conductive structure. The first conductive structure is formed in a first region of a substrate, and includes a first...
8114721 Method of controlling gate thickness in forming FinFET devices  
A method of forming a FinFET device is provided. In one embodiment, a fin is formed on a substrate. A gate structure is formed over the fin, the gate structure having a dielectric layer and a...
8110456 Method for making a self aligning memory device  
A self aligning memory device, with a memory element switchable between electrical property states by the application of energy, includes a substrate and word lines, at least the sides of the word...
8110465 Field effect transistor having an asymmetric gate electrode  
The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that abut each other near the middle of the...
8105907 Manufacturing method of semiconductor memory device  
To provide a manufacturing method of a semiconductor memory device, the method including forming contact plugs to be connected to a drain region or a source region of each of transistors, by using...
8097506 Shallow trench isolation for a memory  
In some embodiments, a gate structure with a spacer on its side may be used as a mask to form self-aligned trenches in a microelectronic memory, such as a flash memory. A first portion of the gate...
8093665 Semiconductor device and method for fabricating the same  
A semiconductor device is described, which includes a substrate, a gate structure, doped regions and lightly doped regions. The substrate has a stepped upper surface, which includes a first...
8088665 Method of forming self-aligned low resistance contact layer  
Embodiments of the present invention describe a method of fabricating low resistance contact layers on a semiconductor device. The semiconductor device comprises a substrate having source and drain...
8088662 Fabrication method of trenched metal-oxide-semiconductor device  
A fabrication method of a trenched metal-oxide-semiconductor device is provided. Firstly, an epitaxial layer is formed on a substrate. Then, a plurality of gate trenches is formed in the epitaxial...
8080459 Self aligned contact in a semiconductor device and method of fabricating the same  
A method of fabricating a self-aligned contact in a semiconductor device, in accordance with one embodiment of the present invention, includes etching a trench in a core area and partially...
8076209 Methods for fabricating MOS devices having highly stressed channels  
Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising...
8058132 Method of fabricating flash memory device  
The present disclosure relates to a method of fabricating a flash memory device. According to the present disclosure, a hard mask layer to which surface roughnesses have been transferred by a metal...
8053347 Method of manufacturing semiconductor device  
A method of manufacturing a semiconductor device, including forming a plurality of gate structures on a substrate, the gate structures each including a hard mask pattern stacked on a gate...
8048751 Method for producing a field effect device having self-aligned electrical connections with respect to the gate electrode  
A gate dielectric, an insulating layer and an etching mask are formed on substrate. The etching mask delineates at least the gate electrode and the source and drain contacts and the source, drain...
8043923 Method of manufacturing semiconductor device  
Methods of manufacturing a semiconductor device include forming a gate electrode on a semiconductor substrate, forming spacers on side walls of the gate electrode, and doping impurities into the...
8030210 Contact barrier structure and manufacturing methods  
A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate...
8022477 Semiconductor apparatus having lateral type MIS transistor  
A semiconductor apparatus comprises: a semiconductor substrate; and a lateral type MIS transistor disposed on a surface part of the semiconductor substrate. The lateral type MIS transistor...
8017489 Field effect structure including carbon alloyed channel region and source/drain region not carbon alloyed  
A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device structure. The field effect device structure includes a gate electrode located over...
8016941 Method and apparatus for manufacturing a semiconductor  
A method and apparatus for crystallizing a semiconductor that includes a first layer having a first crystal lattice orientation and a second layer having a second crystal lattice orientation,...
8012839 Method for fabricating a semiconductor device having an epitaxial channel and transistor having same  
A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an...
8008157 CMOS device with raised source and drain regions  
A method of forming a semiconductor structure includes forming a PMOS device and an NMOS device. The step of forming the PMOS device includes forming a first gate stack on a semiconductor...
7985643 Semiconductor transistors with contact holes close to gates  
A semiconductor structure. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel...
7981740 Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterning  
When forming transistor elements on the basis of sophisticated high-k metal gate structures, the efficiency of a replacement gate approach may be enhanced by more efficiently adjusting the gate...
7977192 Fabrication method of trenched metal-oxide-semiconductor device  
A fabrication method of a trenched metal-oxide-semiconductor device is provided. Firstly, an epitaxial layer is formed on a substrate. Then, a plurality of gate trenches is formed in the epitaxial...
7977180 Methods for fabricating stressed MOS devices  
Methods for fabricating stressed MOS devices are provided. In one embodiment, the method comprises providing a silicon substrate having a P-well region and depositing a polycrystalline silicon gate...
7977177 Methods of forming nano-devices using nanostructures having self-assembly characteristics  
Provided are methods of forming nano-devices. One of the methods includes forming a nano-scale self-assembly material layer on a substrate formed of at least one layer, forming a mask layer on the...
7964487 Carrier mobility enhanced channel devices and method of manufacture  
An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a...
7947557 Heterojunction tunneling field effect transistors, and methods for fabricating the same  
The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate...
7936006 Semiconductor device with backfilled isolation  
An MOS device has an embedded dielectric structure underlying an active portion of the device, such as a source extension or a drain extension. In an alternative embodiment, an embedded dielectric...
7936016 Semiconductor device and manufacturing method thereof  
There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a...
7932144 Semiconductor structure and method of forming the structure  
Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the...
7923338 Increasing stress transfer efficiency in a transistor by reducing spacer width during the drain/source implantation sequence  
By forming a single spacer element and reducing the size thereof by a well-controllable etch process, a complex lateral dopant profile may be obtained at reduced process complexity compared to...
7915129 Method of fabricating high-voltage metal oxide semiconductor transistor devices  
A process of fabricating a transistor employs a relatively thicker sacrificial nitride layer that reduces the time and cost associated with chemical-mechanical polish (CMP) processes by reducing...
7915128 High voltage semiconductor devices  
A transistor suitable for high-voltage applications and a method of manufacture is provided. A first device is formed by depositing a dielectric layer and a conductive layer over a substrate. A...
7910439 Super self-aligned trench MOSFET devices, methods, and systems  
A manufacturing process and design structure for a super self-aligned trench power MOSFET. A plurality of super self-aligned trenches of different depths are formed into the body layer and...
7902029 Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor  
Processes for forming self-aligned, deposited source/drain, insulated gate, transistors and, in particular, FETs. By depositing a source/drain in a recess such that it remains only in the recess,...
7892930 Method to improve transistor tox using SI recessing with no additional masking steps  
A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure is formed comprising a protective...
7888223 Method for fabricating P-channel field-effect transistor (FET)  
A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form...
7888220 Self-aligned insulating etchstop layer on a metal contact  
A semiconductor device comprising a substrate having a transistor that includes a metal gate structure; a first oxide layer formed over the substrate; a silane layer formed on the first oxide...
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