Patents in Class 438/297

Matches 1 - 50 out of 419

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Match	Document	Document Title
1	7608515	Diffusion layer for stressed semiconductor devices A diffusion layer for semiconductor devices is provided. In accordance with embodiments of the present invention, a semiconductor device, such as a transistor, comprises doped regions surrounded by...
2	7601597	Manufacturing method of a super-junction semiconductor device A manufacturing method for a super-junction semiconductor device is disclosed. The method includes a first step of depositing, on a low-resistivity semiconductor substrate of one conductivity type,...
3	7577493	Temperature regulating method, thermal processing system and semiconductor device manufacturing method A temperature regulating method in a thermal processing system includes controlling a heating means by performing integral operation, differential operation and proportional operation by means of a...
4	7566482	SOI by oxidation of porous silicon A method in which a SOI substrate structure is fabricated by oxidation of graded porous Si is provided. The graded porous Si is formed by first implanting a dopant (p- or n-type) into a...
5	7564056	Method for manufacturing a semiconductor device Embodiments relate to a method for manufacturing a semiconductor device. In embodiments, the method may include forming a gate electrode on the semiconductor substrate, forming a pattern having a...
6	7550355	Low-leakage transistor and manufacturing method thereof A boron ion stream may be used to implant ions, such as boron ions, into the sidewalls of an active area, such as an NFET active area. The boron ion stream has both vertical tilt and horizontal...
7	7544574	Methods for discretized processing of regions of a substrate The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of...
8	7521314	Method for selective removal of a layer A method for forming a semiconductor device includes forming a liner over a semiconductor material including a control electrode. The method further includes forming a first spacer adjacent to the...
9	7514332	Semiconductor device and method for manufacturing the same A method for manufacturing a semiconductor device includes the steps of (a) forming a first region by selectively ion-implanting a second conductive type impurity into a first conductive type...
10	7510927	LOCOS isolation for fully-depleted SOI devices The present invention discloses a method including: providing a substrate; forming a buried oxide layer over the substrate; forming a thin silicon body layer over the buried oxide layer, the thin...
11	7504309	Pre-silicide spacer removal A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in...
12	7488647	System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird's beak structure in the manufacture of a semiconductor device A system and method is disclosed that prevents the formation of a vertical bird's beak structure in the manufacture of a semiconductor device. A polysilicon filled trench is formed in a substrate...
13	7482243	Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique The present invention provides a method of forming a thin channel MOSFET having low external resistance. The method comprises forming a dummy gate region atop a substrate; implanting oxide forming...
14	7436030	Strained MOSFETs on separated silicon layers A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are...
15	7425475	Method for fabricating semiconductor device and semiconductor device A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device including a substrate layer including a plurality of first...
16	7384836	Integrated circuit transistor insulating region fabrication method A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate...
17	7371645	Method of manufacturing a field effect transistor device with recessed channel and corner gate device Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench...
18	7338881	Method for manufacturing semiconductor element A method for manufacturing a semiconductor element includes preparing an SOI layer having a transistor forming area and an element isolation area, forming an oxidation-resistant mask layer on the...
19	7335549	Semiconductor device and method for fabricating the same An N-channel transistor includes: an N-type source region, a gate electrode, a P-type body region, an N-type drain offset region, and a drain contact region, which is an N-type drain region. The...
20	7332387	MOSFET structure and method of fabricating the same A MOSFET structure and a method of forming it are described. The thickness of a portion of the gate dielectric layer of the MOSFET structure adjacent to the drain region is increased to form a...
21	7329599	Method for fabricating a semiconductor device Methods are provided for semiconductor devices having low contact resistance. The method in accordance with one embodiment of the invention comprises forming an insulating layer overlying a...
22	7316959	Semiconductor device and method for fabricating the same The semiconductor device comprises a semiconductor layer 18 formed on an insulation layer 16 , a gate electrode 22 formed on the semiconductor layer with a gate insulation film 20 formed...
23	7288828	Metal oxide semiconductor transistor device A metal-oxide-semiconductor (MOS) transistor device is provided. The MOS transistor device includes a substrate, a gate structure, a spacer, a source/drain region and a barrier layer. The gate...
24	7259055	Method of forming high-luminescence silicon electroluminescence device A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO)...
25	7220647	Method of cleaning wafer and method of manufacturing gate structure A method of cleaning a wafer, adapted for a patterned gate structure. The gate structures comprise a gate dielectric layer, a nitrogen-containing barrier layer and a silicon-containing gate layer...
26	7144785	Method of forming isolation trench with spacer formation A strained silicon semiconductor arrangement with a shallow trench isolation (STI) structure has a strained silicon (Si) layer formed on a silicon germanium (SiGe) layer. A trench extends through...
27	7129138	Methods of implementing and enhanced silicon-on-insulator (SOI) box structures Enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods are provided for implementing enhanced SOI BOX structures. An oxygen implant step is performed from a backside into a...
28	7112482	Method of forming a field effect transistor A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides...
29	7091069	Ultra thin body fully-depleted SOI MOSFETs A method of creating ultra tin body fully-depleted SOI MOSFETs in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically...
30	7060579	Increased drive current by isotropic recess etch A method ( 100 ) of forming a transistor includes forming a gate structure ( 108 ) over a semiconductor body and forming recesses ( 112 ) using an isotropic etch using the gate structure as an etch...
31	7060574	Buried channel type transistor having a trench gate and method of manufacturing the same In a method of manufacturing a buried channel type transistor, a trench is formed at a surface portion of a substrate. A first and a second threshold voltage control regions are formed at portions...
32	7045468	Isolated junction structure and method of manufacture A MOSFET structure in which the channel region is contiguous with the semiconductor substrate while the source and drain junctions are substantially isolated from the substrate, includes a...
33	7037792	Formation of removable shroud by anisotropic plasma etch Isotropic etching of sacrificial oxide that is adjacent to a trench fill step in an STI wafer can lead to undesired etching away of a sidewall of the trench fill material (e.g., HDP oxide). A...
34	7026232	Systems and methods for low leakage strained-channel transistor The present invention facilitates semiconductor fabrication by providing methods of fabrication that mitigate leakage and apply strain to channel regions of transistor devices. A semiconductor...
35	7008850	Method for manufacturing a semiconductor device A method for manufacturing the semiconductor device of which a transistor and a MNOS type memory transistor, each of which has a different gate withstand voltage and drain withstand voltage, are...
36	6977205	Method for manufacturing SOI LOCOS MOSFET with metal oxide film or impurity-implanted field oxide This invention provides a semiconductor device with an element isolation implemented by a method of manufacturing a semiconductor device comprising the steps of: forming a pad oxide film 140 and...
37	6955957	Method of forming a floating gate in a flash memory device Disclosed is a method of forming the floating gate in the flash memory device. After the first polysilicon film is deposited on the semiconductor substrate, the trench is formed on the first...
38	6951785	Methods of forming field effect transistors including raised source/drain regions A method of forming a field effect transistor may include forming a doped layer at a surface of a semiconductor substrate, and forming a groove through the doped layer at the surface of the...
39	6933207	Method of forming integrated circuitry Memory integrated circuitry includes an array of memory cells formed over a semiconductive substrate and occupying area thereover, at least some memory cells of the array being formed in lines of...
40	6924199	Method to form flash memory with very narrow polysilicon spacing A new method to form a transistor gate in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A conductor layer is formed overlying the...
41	6921690	Method of fabricating enhanced EPROM structures with accentuated hot electron generation regions An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of...
42	6900101	LDMOS transistors and methods for making the same LDMOS transistor devices and fabrication methods are provided, in which additional dopants are provided to region of a substrate near a thick dielectric between the channel and the drain to reduce...
43	6855602	Method for forming a box shaped polygate A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed...
44	RE38674	Process for forming a thin oxide layer A novel process for forming a robust, sub-100 Å oxide is disclosed. Native oxide growth is tightly controlled by flowing pure nitrogen during wafer push and nitrogen with a small amount of oxygen...
45	6828198	System-on-chip (SOC) solutions with multiple devices by multiple poly gate trimming process A method of forming gate electrode layer portions having differing widths comprising the following steps. A structure having a gate electrode layer and a hard mask layer thereover and including two...
46	6818495	Method for forming high purity silicon oxide field oxide isolation region A method for forming within a silicon semiconductor substrate employed within a microelectronics fabrication a silicon oxide dielectric layer. There is provided a silicon semiconductor substrate....
47	6812533	SOI based bipolar transistor having a majority carrier accumulation layer as subcollector An electronic circuit comprises a bipolar transistor that includes a conductive back electrode, an insulator layer over the conductive back electrode and a semiconductor layer of either an n-type...
48	6812148	Preventing gate oxice thinning effect in a recess LOCOS process Embodiments of the present invention relate to a method for preventing gate oxide thinning in a recess LOCOS process. The plurality of trenches are separated by a patterned pad oxide and a...
49	6797587	Active region corner implantation method for fabricating a semiconductor integrated circuit microelectronic fabrication Within a method for forming an isolation region within a semiconductor substrate, there is, prior to forming the isolation region within an isolation trench formed adjoining an active region of a...
50	6764922	Method of formation of an oxynitride shallow trench isolation An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The...

Matches 1 - 50 out of 419

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