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4580330 |
Integrated circuit isolation
An integrated circuit isolation technology wherein the nitride-sidewall methods of the prior art are improved by performing an undercut and backfill before the second nitride (the sidewall nitride...
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4575920 |
Method of manufacturing an insulated-gate field-effect transistor
A method of manufacturing an insulated-gate field-effect transistor on a silicon substrate at high density for large scale integration is disclosed. The source and drain regions of the transistor...
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4561172 |
Integrated circuit fabrication method utilizing selective etching and oxidation to form isolation regions
A sidewall-nitride isolation technology refines process control over lateral oxide encroachment by preventing any thinning of the nitride moat-masking layer during the nitride etch step which...
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4560582 |
Method of preparing a semiconductor device
A semiconductor device including a MOS field effect transistor formed on a single silicon crystal substrate having source and drain diffused regions of reduced depth. In order to avoid penetration...
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4541167 |
Method for integrated circuit device isolation
The disclosure relates to a method manufacturing semiconductor devices which minimizes encroachment by utilizing a polycrystalline silicon (polysilicon) layer over a grown oxide on the substrate...
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4538343 |
Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking
A sidewall-nitride isolation technology avoids stress-induced defects, while permitting a heavy channel stop implant to avoid turn-on of the field oxide transistor, by performing a two-step silicon...
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4523213 |
MOS Semiconductor device and method of manufacturing the same
An MOS semiconductor device, wherein a buried region of silicon oxide or silicon nitride extends partly over the bottom plane of the channel region of an MOS transistor.
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4520553 |
Process for manufacturing an integrated insulated-gate field-effect transistor
A process is described for manufacturing integrated insulated-gate field-effect transistors comprising contacts on both the source region and the drain region which are self-aligned with respect to...
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4517729 |
Method for fabricating MOS device with self-aligned contacts
A method for fabricating an integrated circuit semiconductor device comprised of an array of MOSFET elements having self-aligned or self-registered connections with conductive interconnect lines....
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4510670 |
Method for the manufacture of integrated MOS-field effect transistor circuits silicon gate technology having diffusion zones coated with silicide as low-impedance printed conductors
A method for the manufacture of integrated MOS-field effect transistor circuits in silicon gate technology and wherein diffusion source and drain zones are coated with a high melting point silicide...
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4506437 |
Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and...
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4487639 |
Localized epitaxy for VLSI devices
A method of forming a semiconductor device having a single crystal silicon substrate, the surface of which includes exposed silicon areas bounded by and coplanar with insulating oxide regions. A...
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4486942 |
Method of manufacturing semiconductor integrated circuit BI-MOS device
A method of manufacturing a semiconductor integrated circuit of the BI-MOS type on a common semiconductor substrate comprising forming an oxide film by thermal oxidation to isolate the elements and...
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4464824 |
Epitaxial contact fabrication process
A process for fabricating an electrical contact which connects an epitaxial layer, well, or substrate with a metallic interconnect layer during the course of creating active integrated circuit...
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4461072 |
Method for preparing an insulated gate field effect transistor
Disclosed here is an IGFET formed on the single crystal silicon substrate where the major plane surface is deviated within the range from 22 degree to 34 degree toward the crystallographic surface...
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4460413 |
Method of patterning device regions by oxidizing patterned aluminum layer
A pattern utilized to prepare a diffraction grating, or an element of a semiconductor device, for example a silicon island, or a device isolation pattern or a semiconductor element, such as a MOS...
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4458407 |
Process for fabricating semi-conductive oxide between two poly silicon gate electrodes
A process for placing non-continuous Dual Electron Injection Structures (DEIS) between two layers of polysilicon used to form an array of poly devices on an integrated circuit substrate. Separate...
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4445267 |
MOSFET Structure and process to form micrometer long source/drain spacing
A method for fabricating a semiconductor integrated circuit structure having sub-micrometer gate length field effect transistor devices is described wherein a surface isolation pattern is formed in...
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4442589 |
Method for manufacturing field effect transistors
A transistor and method of forming the same are disclosed. A thick mesa of dielectric material is grown on a semiconductor substrate and two or more layers of polycrystalline silicon grown on the...
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4441247 |
Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate
A process is described for forming MOS circuits which include underlying polysilicon members such as gate members covered with metal. In one embodiment, a self-aligning tungsten process is used to...
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4432133 |
Method of producing a field effect transistor
A method for producing a MOSFET which includes the steps of forming a thick insulating layer having an inclined surface and surrounding the active region of a semiconductor substrate, forming a...
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4430791 |
Sub-micrometer channel length field effect transistor process
A method for fabricating a semiconductor integrated circuit structure having a sub-micrometer length device element is described wherein a surface isolation pattern is formed in a semiconductor...
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4420872 |
Method of manufacturing a semiconductor device
A method of manufacturing an integrated circuit having at least an insulated gate field effect transistor (IGFET). Provided on the silicon surface are successively a gate oxide layer and a doped...
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4375993 |
Method of producing a semiconductor device by simultaneous multiple laser annealing
A method of producing a semiconductor device which comprises steps of forming an insulator layer on a semiconductor substrate, forming a semiconductor layer on the insulator layer and then...
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4372031 |
Method of making high density memory cells with improved metal-to-silicon contacts
Semiconductor read only memory (ROM) or electrically programmable memory (EPROM) devices are constructed using a metal-to-silicon contact arrangement which provides small cell size. An intervening...
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4364166 |
Semiconductor integrated circuit interconnections
An improved interconnection for semiconductor integrated circuits is provided by a member made of doped polycrystalline silicon and metal silicide that provides the simultaneous advantages of high...
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4359816 |
Self-aligned metal process for field effect transistor integrated circuits
A process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistors. The insulation between the...
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4357747 |
Method for producing a semiconductor device having an insulated gate type field effect transistor
An insulated gate type field effect transistor forming one cell of a high density integrated circuit semiconductor memory device and a method for producing the same are disclosed. A channel stopper...
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4348802 |
Process for producing a semiconductor device
In a process for producing a semiconductor device, particularly an MIS structure semiconductor device, an electrode, which is in ohmic contact with the semiconductor substrate, is usually formed on...
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4343078 |
IGFET Forming method
An insulated-gate field effect transistor for high speed operation is disclosed in which the internal resistance of the gate electrode is reduced and the stray gate capacitance is maintained at a...
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4341009 |
Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate
A buried electrical contact is made to a substrate of monocrystalline silicon through a relatively thin layer of silicon dioxide without causing damage to the relatively thin layer of silicon...
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4333225 |
Method of making a circular high voltage field effect transistor
A circular high voltage field effect transistor suitable for inclusion in LSI circuits, and the process for making said transistor, are described. The transistor comprises a central drain and...
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4329706 |
Doped polysilicon silicide semiconductor integrated circuit interconnections
An improved interconnection for semiconductor integrated circuits is provided by a member made of doped polycrystalline silicon and metal silicide that provides the simultaneous advantages of high...
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4317276 |
Method of manufacturing an insulated gate field-effect transistor therefore in a silicon wafer
A method of manufacturing a device in a wafer with a P-type semiconductor, includes forming on a surface of the semiconductor body a layer of silicon dioxide doped with an N-type dopant. The...
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4313256 |
Method of producing integrated MOS circuits via silicon gate technology
A method of producing integrated MOS circuits via silicon gate technology with self-adjusting contacts by using silicon nitride masking. In accordance with this method, after etching contact holes...
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4288910 |
Method of manufacturing a semiconductor device
A method of manufacturing devices in a semiconductor body 20 of a first conductivity type. An oxygen impervious masking medium 22 is placed on the body 20. Portions of the medium 22 are removed to...
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4282647 |
Method of fabricating high density refractory metal gate MOS integrated circuits utilizing the gate as a selective diffusion and oxidation mask
A method for fabricating an MOS integrated circuit having a refractory metal gate structure includes the formation of an insulating layer and a conductive refractory metal layer on a substrate,...
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4280271 |
Three level interconnect process for manufacture of integrated circuit devices
An improved MOS device and method of making it are provided which utilize basically the standard N-chanel self-aligned silicon gate structure and process with implants for self-alignment, modified...
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4277881 |
Process for fabrication of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and...
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4265685 |
Utilizing simultaneous masking and diffusion of peripheral substrate areas
The present invention deals with a method of taking out a substrate electrode of a LOCOS-type silicon gate MOSIC device from the surface of the semiconductor substrate. According to the present...
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4234362 |
Method for forming an insulator between layers of conductive material
A method for forming an insulator between conductive layers, such as highly doped polycrystalline silicon, that involves first forming a conductive layer of, for example, polycrystalline silicon on...
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4231051 |
Process for producing minimal geometry devices for VSLI applications utilizing self-aligned gates and self-aligned contacts, and resultant structures
A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for diffused conducting lines in the substrate. Mask...
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4221044 |
Self-alignment of gate contacts at local or remote sites
A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and...
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4221045 |
Self-aligned contacts in an ion implanted VLSI circuit
A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and...
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4216573 |
Three mask process for making field effect transistors
A three mask method is provided for making a field effect transistor which includes the use of a first mask for defining first and second spaced apart diffusion regions, each having first and...
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4210993 |
Method for fabricating a field effect transistor
A field effect transistor is fabricated by forming a silicon dioxide film having a region where said silicon dioxide film becomes thinner at that area on one surface of a silicon semiconductor...
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4208781 |
Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer
Resistor elements for MOS integrated circuits are made by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The resistor elements are in a part of a polycrystalline...
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RE30251 |
Semiconductor device comprising an insulated gate field effect transistor and method of manufacturing the same
Method of making an insulated gate field effect transistor is described in which the surface of a silicon semiconductor is covered in whole or in part with a layer of a masking material which masks...
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4181537 |
Method of fabricating an insulated gate field effect device
This invention provides a method of making an improved gate structure in which the gate electrode is self-aligned with respect to the field isolation oxide regions. Gate constituting layers are...
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4179311 |
Method of stabilizing semiconductor device by converting doped poly-Si to polyoxides
A method for making a semiconductor device is described in which polycrystalline silicon is vacuum deposited and then converted to silicon dioxide thereby providing a number of advantages over...
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