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5773337 Method for forming ultra-shallow junction of semiconductor device  
There is disclosed a method for forming an ultra-shallow junction of a semiconductor device, comprising a four-stage RTA process following the ion implantation of dopants for source/drain junction,...
5770464 Method for fabricating semiconductor devices having lightly doped drain  
A method for fabricating a semiconductor device comprises the steps of depositing polysilicon on a semiconductor substrate for a gate electrode and word line and then depositing insulating oxide...
5766965 Semiconductor device and method of manufacturing the same  
A diffused layer serves as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the...
5763309 Self-aligned isolation and planarization process for memory array  
A self-aligned planarization and isolation technique achieves smaller dimension memory cells using self-aligned isolation trenches. The process involves defining the lines of buried diffusion and...
5747356 Method for manufacturing ISRC MOSFET  
The present invention privides a method for manufacturing an ISRC MOSFET, comprising steps of forming an isolating layer through the LOCOS process, depositing a mask oxide layer, exposing only the...
5733794 Process for forming a semiconductor device with ESD protection  
A semiconductor device with an electrostatic discharge (ESD) protection transistor is devised, wherein the ESD protection transistor has halo regions of an opposite conductivity type from the...
5733812 Semiconductor device with a field-effect transistor having a lower resistance impurity diffusion layer, and method of manufacturing the same  
There is formed an isolation which surrounds an active region of a semiconductor substrate. Formed over the active region and on the isolation, respectively, are a gate electrode and two gate...
5728619 Selective reactive Ion etch (RIE) method for forming a narrow line-width high aspect ratio via through an integrated circuit layer  
A method for forming within an integrated circuit a narrow line-width high aspect ratio via through a first integrated circuit layer which resides upon a second integrated circuit layer. There is...
5728609 Method for producing contact holes  
A method for producing contact holes in MOS integrated circuits by the SOI technique, with an oxide layer and a silicon layer above it, includes producing raised contact hole regions on an...
5728620 Isolation method of semiconductor device  
A device isolation method divides a semiconductor substrate into active and inactive regions. A first device isolation layer is formed in a first inactive region using a trench isolation method....
5721174 Narrow deep trench isolation process with trench filling by oxidation  
The invention is a process for filling narrow isolation trenches with thermal oxide using a nitride spacer and a second trench etch. The method begins by providing forming a pad oxide layer 20 and...
5721146 Method of forming buried contact architecture within a trench  
An method for the fabrication of an improved polysilicon buried contact is described. The contact is formed within a trench etched into the silicon substrate. The effective area of the contact is...
5714410 Method for fabricating CMOS analog semiconductor  
An improved CMOS analog semiconductor apparatus and a fabrication method thereof which are capable of selectively oxidizing a polysilicon, and forming a conductive region and an insulation region...
5712183 Method of fabricating a via for an SRAM device  
A method of fabricating a via, that reduces contact resistance between two conductive layers. A conductive layer is formed at the periphery of a top surface of a gate. An insulating layer is formed...
5712173 Method of making semiconductor device with self-aligned insulator  
A semiconductor device having the advantages of an SOI structure without the attendant disadvantages is obtained by implanting oxygen ions using the gate electrode as a mask, and heating to form...
5698461 Method for fabricating lightly doped drain metal oxide semiconductor field effect transistor  
A lightly doped drain (LDD) metal oxide semiconductor field effect transistor (MOSFET). Field oxide is used as a hard mask for a total-overlap polysilicon (TOP) gate which minimizes hot-carrier...
5691212 MOS device structure and integration method  
This invention describes a new method for forming self-aligned silicide for application in MOSFET, and a new structure of MOSFET device featuring elevated source and drain, with the objectives of...
5683922 Method of fabricating a self-aligned contact  
A method of forming a self-aligned contact for a transistor formed on a substrate. A self-aligned silicide layer is formed on the surface of a source/drain region of the transistor. A silicon...
5683921 Semiconductor device and method of manufacturing the same  
A MOS transistor consists of a gate insulating film, a gate electrode, a pair of sidewall spacers on the side faces of the gate electrode, lightly doped source/drain regions, and heavily doped...
5681769 Method of fabricating a high capacitance insulated-gate field effect transistor  
A high capacitance field effect transistor for use in an integrated memory circuit is fabricated with an optimized gate electrode and active region overlap, increasing the gate electrode to...
5679589 FET with gate spacer  
A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adjacent double or triple layered gate spacers. The spacers permit...
5677249 Semiconductor apparatus and production method for the same  
A gate wire is formed so as to extend from an active area to a separation, and an impurity diffused area is formed on each side of the gate electrode located on the active area. A contact member...
5677214 Raised source/drain MOS transistor with covered epitaxial notches and fabrication method  
The invention provides a technique for forming a MOS transistor with reduced leakage current and a shorter channel length between source and drain electrodes. The transistor includes a gate...
5674760 Method of forming isolation regions in a MOS transistor device  
The present invention is directed to a MOS transistor and its method of fabrication. The transistor includes isolating layers below source/drain regions of the transistor. In this manner, lateral...
5665623 Method of fabricating totally self-aligned contacts for dynamic randomaccess memory cells  
A method is provided for fabricating totally self-aligned contacts on semiconductor substrates. The method is particularly applicable to dynamic random access memory for reducing the cell area. The...
5652160 Method of fabricating a buried contact structure with WSi.sub.x sidewall spacers  
A method of forming WSi x sidewall spacers as an etching stop in the fabrication process of a buried contact. After a gate dielectric layer and a first conducting layer are formed over a...
5646435 Method for fabricating CMOS field effect transistors having sub-quarter micrometer channel lengths with improved short channel effect characteristics  
A reverse self-aligned field effect transistor having sub-quarter micrometer (<0.25 um) channel lengths and shallow source/drain junction depths was achieved. The method for fabricating the FET...
5620911 Method for fabricating a metal field effect transistor having a recessed gate  
A method for fabricating a metal oxide semiconductor field effect transistor, capable of achieving a reduction in topology by forming a trench on a silicon substrate by use of a temporary field...
5612249 Post-gate LOCOS  
A method of defining a local oxidation of silicon (LOCOS) field isolation process after a poly gate is deposited. A gate oxide is grown on a silicon substrate, and then poly or amorphous silicon is...
5612240 Method for making electrical connections to self-aligned contacts that extends beyond the photo-lithographic resolution limit  
A method was achieved for making electrical connections to FET self-aligned source/drain areas extending the limits of the photolithographic resolution and relaxing the alignment tolerance. FET...
5607884 Method for fabricating MOS transistor having source/drain region of shallow junction and silicide film  
A method for fabricating an MOS transistor having a source/drain region of shallow junction and a thin silicide film is disclosed. The present method takes advantage of the phase separation of the...
5604157 Reduced notching of polycide gates using silicon anti reflection layer  
A method for fabricating MOSFET devices, with narrow gate structures, and narrow spaces between gate structures, has been developed. The addition of a rough surfaced silicon layer, as part of the...
5595920 Method of manufacturing a semiconductor memory device for use with image pickup  
A semiconductor memory device includes: an insulated gate transistor having a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between...
5593928 Method of making a semiconductor device having floating source and drain regions  
The present invention relates to a MOS transistor having floating source regions and floating drain regions. An epitaxial layer is grown on the channel regions of a semiconductor substrate in such...
5593911 Method of making ESD protection circuit with three stages  
An MOS electrostatic discharge, ESD, protection circuit for protecting semiconductors from ESD damage is formed on a doped silicon substrate. The circuit includes three stages. The first stage...
5585294 Method of fabricating lateral double diffused MOS (LDMOS) transistors  
A process for the fabrication of an improved LDMOS transistor, and such an improved LDMOS transistor are provided. The improved LDMOS transistor is in a semiconductor layer of a first conductivity...
5583064 Semiconductor device and process for formation thereof  
A recess is formed (dug) into the surface of a substrate to form a gate channel in the recess, so that a monocrystalline source/drain region can be formed at a level higher than that of the...
5580806 Method of fabricating a buried contact structure for SRAM  
A buried contact structure formed on a semiconductor substrate. A single polysilicon layer is formed on a field oxide layer. The polysilicon layer is patterned and etched to form an interconnect...
5576230 Method of fabrication of a semiconductor device having a tapered implanted region  
A semiconductor device includes implanted regions (54) formed in a semiconductor layer (12). The implanted regions (54) are self-aligned with field oxide regions (20) and a gate structure (25) and...
5576226 Method of fabricating memory device using a halogen implant  
A method of fabricating a memory device for improving the reliability of the cell area and the driving capability of the peripheral area is disclosed, wherein the method comprises the steps of...
5573965 Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology  
The base layer of high quality spacers, such as those used on the sidewalls of the gate stack of submicron devices (e.g., MOSFETs, EPROMs), are formed as composite, multi-layered structures of...
5563096 Semiconductor device fabrication with planar gate interconnect surface  
In accordance with principles of the invention, there is provided a new process for semiconductor device fabrication. The disclosed process includes forming field isolation regions on a surface of...
5547884 Method of manufacturing a semiconductor memory device having a common source region  
Field oxide films are formed on a semiconductor substrate of first conductivity type to be spaced from each other in the stripe shape. Gate insulating films are formed on the semiconductor...
5545574 Process for forming a semiconductor device having a metal-semiconductor compound  
A metal-semiconductor compound (72, 74, 76) is formed after a step that introduces nitrogen into regions (52, 54, 56) of the device (100). In one embodiment, a nitrogen-containing gas is exposed to...
5545579 Method of fabricating a sub-quarter micrometer channel field effect transistor having elevated source/drain areas and lightly doped drains  
A reverse self-aligned field effect transistor having sub-quarter micrometer (<0.25 um) channel lengths, lightly doped source/drain, and shallow junction depths was achieved. The method for...
5525552 Method for fabricating a MOSFET device with a buried contact  
A process for fabricating MOSFET devices, using an optimized buried contact approach, has been developed. The process includes the provision of thermal oxide (10) and polysilicon spacer (12)...
5523250 Method of manufacturing a MOSFET with LDD regions  
This invention relates to a method of manufacturing a MOSFET with LDD regions, high integrated semiconductor, wherein a photoresist pattern for a source/drain implant mask is formed to sufficiently...
5512508 Method and apparatus for improvement of interconnection capacitance  
A method and apparatus for reducing interconnection capacitance. A lightly doped buried layer is provided in or on a substrate below a field oxide region. The capacitance of an interconnect on the...
5500391 Method for making a semiconductor device including diffusion control  
A process for making a MOS device on a silicon substrate includes the step of forming a buried layer of germanium-silicon alloy in the substrate, or, alternatively, a buried layer of silicon...
5496750 Elevated source/drain junction metal oxide semiconductor field-effect transistor using blanket silicon deposition  
The described embodiments of the present invention provide a method for fabricating elevated source/drain junction metal oxide semiconductor field-effect transistors. The process does not require...
Matches 201 - 250 out of 420 < 1 2 3 4 5 6 7 8 9 >