Matches 151 - 200 out of 420 < 1 2 3 4 5 6 7 8 9 >
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6071779 Source line fabrication process for flash memory  
A method of fabricating a semiconductor device having a memory array (9) that includes a source line (24) is provided. The method of forming the source line (24) may include providing a...
6069055 Fabricating method for semiconductor device  
The fabricating method for semiconductor devices in which the trench technique is employed to perform isolation between devices, and which comprises the steps of sequentially depositing a first...
6066549 Semiconductor processing method of forming a conductive gate line and semiconductor processing method of making ohmic contact between a transistor gate line and a substrate diffusion region  
A semiconductor processing method of forming a conductive gate line includes forming a field oxide mask over a portion of a semiconductor substrate. Field oxide regions are formed adjacent the...
6066545 Birdsbeak encroachment using combination of wet and dry etch for isolation nitride  
A technique for reducing active area encroachment (birdsbeak) by using a polysilicon hard mask combined with both wet and dry etch for the isolation nitride. This process forms a thinner layer of...
6063674 Method for forming high voltage device  
A method for forming high voltage devices is provided. A P-type semiconductor substrate is provided. An oxide layer is formed on the P-type semiconductor substrate. A first P-well and a second...
6060372 Method for making a semiconductor device with improved sidewall junction capacitance  
A semiconductor device (10) of the present invention has a gate (32) insulatively disposed above the substrate, source and drain regions (36, 38) disposed near the surface in the substrate adjacent...
6057197 Isolation scheme to prevent field oxide edge from oxide loss  
A semiconductor integrated circuit such as a flash memory device with a novel isolation structure. Field isolation (130) is defined on a substrate (10). A spacer (107) is formed at the edges of the...
6048756 Method for making a silicon-on-insulator MOS transistor using a selective SiGe epitaxy  
Disclosed is a method for manufacturing a metal-oxide-semiconductor (MOS) device formed in an epitaxial silicon layer on insulator substrate comprising the steps of forming a field oxide layer...
6040221 Semiconductor processing methods of forming a buried contact, a conductive line, an electrical connection to a buried contact area, and a field effect transistor gate  
A semiconductor processing method of forming a field effect transistor gate over a semiconductor substrate includes forming a gate dielectric layer over substrate active area while a buried contact...
6033960 Method to improve the breakdown voltage of P-channel devices  
A P-channel MOS device having an elevated breakdown voltage is created without increasing device size or requiring additional fabrication steps. During the P-field implant step, P type dopant is...
6020251 Method of forming buried diffusion junctions in conjunction with shallow-trench isolation structures in a semiconductor device  
A method is provided for use in a semiconductor fabrication process to form buried diffusion junctions in conjunction with shallow-trench isolation (STI) structures in a semiconductor device. This...
6013560 Semiconductor processing methods of forming field oxidation regions on a semiconductor substrate  
A semiconductor processing method of forming field oxide regions includes, a) providing a sacrificial pad oxide layer over a semiconductor substrate; b) providing a Ge x Si y layer over the pad...
6010949 Method for removing silicon nitride in the fabrication of semiconductor devices  
A method for use in the fabrication of semiconductor devices in accordance with the present invention includes providing a silicon nitride region and oxidizing a region of material in proximity to...
5998274 Method of forming a multiple implant lightly doped drain (MILDD) field effect transistor  
A multiple implant lightly doped drain ("MILDD") field effect transistor is disclosed. The transistor includes a channel, a gate, a dielectric structure that separates the gate from the channel, a...
5994203 Process for stress reduction in silicon during field isolation  
A new polysilicon-buffered field isolation process provides reduced stress during field oxidation and reduced bird's beak. Prior to forming the LOCOS masking stack conventionally used for field...
5985734 Method for fabricating a semiconductor device  
A semiconductor device is disclosed, together with a fabricating method therefor. The semiconductor device has an etch barrier structure, made with SiN or SiON, which is formed on an...
5981359 Method of manufacturing semiconductor device having isolation film on SOI substrate  
Disclosed is a method of manufacturing a semiconductor device having a reliable element isolation insulating film on an SOI substrate having an SOI layer. That is, the step of forming a...
5976927 Two mask method for reducing field oxide encroachment in memory arrays  
A method for forming a field oxide isolation regions of a memory array is described. The field isolation regions comprise a rectangular array of oxide islands. The oxide islands are formed by a two...
5972759 Method of making an integrated butt contact having a protective spacer  
The present invention provides a structure and method of forming a butting contact having protective spacers 50A that prevent shorting between a second polysilicon layer 60 and the substrate in a...
5970329 Method of forming power semiconductor devices having insulated gate electrodes  
Methods of forming power semiconductor devices include the steps of forming an insulated gate electrode on a face of semiconductor substrate containing a body region of first conductivity type...
5966627 In-situ doped silicon layers  
A method and apparatus for the manufacture of integrated circuits including the placement of a single tube for introduction of dopant gases into a process chamber is disclosed.
5966618 Method of forming dual field isolation structures  
A method of providing thick and thin oxide structures reduces step changes between a core region and a peripheral region on an integrated circuit. Thin LOCOS structures are provided in a core...
5966619 Process for forming a semiconductor device having a conductive member that protects field isolation during etching  
A semiconductor device (150) is formed having a first conductive member (64) overlying a field isolation region (36) that is typically less than two microns wide. Typically, the field isolation...
5958505 Layered structure with a silicide layer and process for producing such a layered structure  
A process for producing a layered structure in which a silicide layer on a silicon substrate is subjected to local oxidation to cause the boundary layer side of the silicide layer to grow into the...
5956589 Method of forming narrow thermal silicon dioxide side isolation regions in a semiconductor substrate and MOS semiconductor devices fabricated by this method  
A method is disclosed for forming narrow thermal silicon dioxide side isolation regions in a semiconductor substrate and MOS or CMOS semiconductor devices fabricated by this method. A thin...
5953604 Methods for making compact P-channel/N-channel transistor structure  
A structure for a complementary field effect transistor includes a semiconductor body having a first body region of a first conductivity type and an adjoining second body region of an opposite...
5950095 Semiconductor memory cell fabrication method  
A semiconductor device includes a substrate having an active region between field oxide films, a gate formed on the substrate with a gate oxide therebetween, and a first impurity region formed...
5930614 Method for forming MOS device having field shield isolation  
A first conductor for a field shield and a first insulating film are sequentially formed in a predetermined shape on a major surface of a P-type semiconductor substrate through an insulating film....
5927992 Method of forming a dielectric in an integrated circuit  
A method is provided for forming an improved device dielectric of a semiconductor integrated circuit, and an integrated circuit formed according to the same. For scaling geometries for use in the...
5920784 Method for manufacturing a buried transistor  
A method for manufacturing a buried transistor, which includes the steps of forming a field oxide layer in a substrate, the field oxide region having a central portion having a greater thickness...
5913122 Method of making high breakdown voltage twin well device with source/drain regions widely spaced from FOX regions  
An FET semiconductor device comprises a doped silicon semiconductor substrate having surface. The substrate being doped with a first type of dopant. An N-well is formed within the surface of the...
5913136 Process for making a transistor with self-aligned source and drain contacts  
The invention relates to a process for making a transistor with self-aligned contact points and comprises the following steps: formation of multiple layers on a substrate (100) and etching of the...
5908308 Use of borophosphorous tetraethyl orthosilicate (BPTEOS) to improve isolation in a transistor array  
Controlling the thickness of borophosphorous tetraethyl orthosilicate (BPTEOS) used as all or part of the first inter-layer dielectric (ILD0) in manufacturing a semiconductor device containing an...
5895257 LOCOS field oxide and field oxide process using silicon nitride spacers  
A field oxide region and method of forming a field oxide region using a LOCOS process and nitride spacers formed on the sidewalls of the field oxide regions. During the LOCOS process recesses are...
5895237 Narrow isolation oxide process  
A high performance CMOS process using grown field oxide for active area isolation takes advantage of process steps used in LDD transistor fabrication to reduce the chip space occupied by the field...
5885878 Lateral trench MISFET and method of manufacturing the same  
To provide a lateral MISFET that has a uniform and reliable gate insulation film, and exhibits low on-resistance and excellent balance between the breakdown voltage and on-resistance. The device of...
5879992 Method of fabricating step poly to improve program speed in split gate flash  
A method is provided for forming a split-gate flash memory cell having a step poly supporting an interpoly oxide of varying thickness for the purposes of improving the over-all performance of the...
5877069 Method for electrochemical local oxidation of silicon  
A method for electrochemical local oxidation of silicon of selected regions of a silicon substrate of a semiconductor wafer avoids the formation of bird's beak structures of the prior art. The...
5877068 Method for forming isolating layer in semiconductor device  
A method for forming an isolating layer in a semiconductor device includes the steps of forming a first material layer on an active layer having a major axis and a minor axis, forming a second...
5863823 Self-aligned edge control in silicon on insulator  
An improved process and structure for channel stop in silicon on insulator using LOCOS isolation are disclosed. Advantages include decreased ion dose requirements; reduced processing time; smaller...
5858842 Methods of forming combined trench and locos-based electrical isolation regions in semiconductor substrates  
Methods of forming electrical isolation regions in semiconductor substrates include the steps of forming a first electrical isolation region at a face of a semiconductor substrate, then forming a...
5858830 Method of making dual isolation regions for logic and embedded memory devices  
A method for forming thick field oxide regions, to be used for isolation in MOSFET memory regions, while also forming insulator filled, narrow trenches, to be used for isolation purposes in MOSFET...
5856003 Method for forming pseudo buried layer for sub-micron bipolar or BiCMOS device  
A process is described for forming a heavily doped buried element below an active device region of a silicon wafer without the use of costly epitaxial layers and without incurring ion implantation...
5856215 Method of fabricating a CMOS transistor  
The present invention relates to a method of fabricating a CMOS transistor which can further reduce the size of a chip since it is not necessary to consider the metal contact process margin since a...
5854112 Transistor isolation process  
In the manufacture of semiconductor devices on a single substrate, said devices comprising a source region, a drain region and a gate therebetween, forming an isolation region after formation of...
5851901 Method of manufacturing an isolation region of a semiconductor device with advanced planarization  
A semiconductor device manufacturing method of forming an isolation region of a semiconductor device with high planarization is provided. A semiconductor device is formed by forming a mask over a...
5837378 Method of reducing stress-induced defects in silicon  
A process for reducing stress during processing of semiconductor wafers comprising the steps of depositing a masking stack on a top and a bottom surface of the wafer and then removing at least a...
5831320 High voltage metal oxide silicon field effect transistor  
A manufacturing method of high voltage MOSFET includes a process forming the first and second conductive wells in a semiconductor substrate; process forming drift areas in the first and second...
5814551 Methods for forming integrated circuit isolation layers using oxygen diffusing layers  
A method for forming an integrated circuit isolation layer includes the steps of forming a patterned masking layer of a semiconductor substrate, forming an oxygen diffusing layer on the patterned...
5804846 Process for forming a self-aligned raised source/drain MOS device and device therefrom  
The present invention is directed to a process for forming a self-aligned raised source/drain MOS device comprising a planarized metal layer, preferably tungsten, overlying a source, a drain, and a...
Matches 151 - 200 out of 420 < 1 2 3 4 5 6 7 8 9 >