Matches 401 - 450 out of 638 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >
Match Document Document Title
6274434 Method of making memory cell with shallow trench isolation  
In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode,...
6271093 Methods for reducing anomalous narrow channel effect in trench-bounded buried-channel p-MOSFETs  
Methods of manufacturing trench-bounded buried-channel p-type metal oxide semiconductor field effect transistors (p-MOSFETs), as used in dynamic random access memory (DRAM) technologies, for...
6268264 Method of forming shallow trench isolation  
A method of fabricating a shallow trench isolation. A trench is formed in a substrate. An insulation plug is formed to fill the trench. The trench has an exposed upper portion above the substrate....
6265271 Integration of the borderless contact salicide process  
A method for integrating salicide and borderless contact processes while avoiding current leakage at the shallow trench isolation edge is described. Shallow trench isolation (STI) regions are...
6265285 Method of forming a self-aligned trench isolation  
A method of forming a self-aligned trench isolation comprises forming a silicon film on a pad oxide that is grown upon a semiconductor substrate, and then etching the silicon film to expose the pad...
6265284 Method of manufacturing a trench isolation region in a semiconductor device  
A method of manufacturing a semiconductor device in which a groove is not formed at edges of a trench isolation region is provided. The semiconductor device includes an active region and a trench...
6265282 Process for making an isolation structure  
A novel shallow-trench isolation (STI) structure and process for forming it is described. More particularly, a recess is formed in a semiconductor substrate. An oxide layer is formed in the recess...
6261905 Flash memory structure with stacking gate formed using damascene-like structure  
A flash memory cell and the making thereof is disclosed where the cell has a damascene-like stacked gate. The stacked gate is formed not by blanket depositing a first polysilicon layer and then...
6261924 Maskless process for self-aligned contacts  
A method for forming self-aligned borderless contacts without a masking process, in accordance with the invention, includes forming a shallow trench isolation region about an active area region and...
6255176 Method of forming trench for semiconductor device isolation  
A method of forming a trench for semiconductor device isolation includes the steps of making a trench at a device isolation area of a silicon wafer overlaid with a pad oxide and a nitride through...
6251749 Shallow trench isolation formation with sidewall spacer  
An isolation structure which protrudes above the semiconductor surface and sidewall spacers which smooth the topography over said isolation structure.
6251747 Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices  
A method of forming a semiconductor device minimizes oxide recessing in a trench of a semiconductor device. In one embodiment, forming a nitride spacer surrounding the top trench corner oxide in a...
6251734 Method for fabricating trench isolation and trench substrate contact  
A method of manufacturing semiconductor components includes etching two trenches (105, 106, 805, 806, 1205, 1206) into a surface of a substrate (101, 801, 1201), lining the two trenches (105, 106,...
6251746 Methods of forming trench isolation regions having stress-reducing nitride layers therein  
Methods of forming trench isolation regions include the steps of forming a trench masking layer comprising a first material (e.g., polysilicon) on a semiconductor substrate and then etching a...
6248636 Method for forming contact holes of semiconductor memory device  
A novel method for forming contact holes is disclosed. According to the present invention, a silicon substrate is prevented from being over-etched by performing a two-step etching process. The...
6245638 Trench and gate dielectric formation for semiconductor devices  
Semiconductor device fabrication techniques which integrate the formation of trench isolation areas and gate insulating layers are provided. The fabrication techniques include forming one or more...
6235589 Method of making non-volatile memory with polysilicon spacers  
Sidewall spacers comprised of a second polycrystalline silicon film are formed on the sides of a first polycrystalline silicon film in such a way that a relationship of b≤a=x<c/2 is satisfied...
6235608 STI process by method of in-situ multilayer dielectric deposition  
A process for forming shallow trench isolation (STI) structures. It includes the steps of: (a) depositing a composite silicon nitride on to the silicon substrate; (b) forming a shallow trench on...
6228708 Method of manufacturing high voltage mixed-mode device  
A method is described for manufacturing a high voltage mixed-mode device. The method comprises the steps of providing a substrate, wherein the substrate comprises an isolation region, a first...
6228713 Self-aligned floating gate for memory application using shallow trench isolation  
A method to make a self-aligned floating gate in a memory device. The method patterns the floating gate (FG) using the trench etch for the shallow trench isolation (STI). Because the floating gate...
6228742 Method of fabricating shallow trench isolation structure  
A method of fabricating a shallow trench isolation structure is described. A mask layer is formed on the substrate. The mask layer and the substrate are patterned to form trenches in the substrate....
6228727 Method to form shallow trench isolations with rounded corners and reduced trench oxide recess  
A method of fabricating shallow trench isolations has been achieved. A semiconductor substrate is provided. A pad oxide layer is grown overlying the semiconductor substrate. A silicon nitride layer...
6228721 Fabrication of metal oxide structures with different thicknesses on a semiconductor substrate  
For fabricating a metal oxide structure on a semiconductor substrate, an active device area surrounded by at least one STI (shallow trench isolation) structure is formed in the semiconductor...
6225171 Shallow trench isolation process for reduced for junction leakage  
A method of forming shallow trench isolation that reduces junction leakage at the boundary of shallow trench isolation and contact metallurgy of adjacent transistors and that avoids a reduction of...
6214690 Method of forming a semiconductor device having integrated electrode and isolation region formation  
The present invention generally provides a semiconductor device and fabrication process in which gate electrode formation is integrated with the formation of isolation regions. Consistent with one...
6211012 Method of fabricating an ETOX flash memory  
A method of fabricating an ETOX flash memory. A low-resistance source line is formed on the substrate to string each source region in one source array by self-aligned process to substitute...
6211002 CMOS process for forming planarized twin wells  
This invention proposes a process to form planarized twin-wells for CMOS devices. After depositing pad oxide and a silicon nitride layers, a high-energy phosphorus ion implantation is performed to...
6207533 Method for forming an integrated circuit  
In one embodiment, a first dielectric layer (16) is formed overlying a semiconductor substrate (4). A portion of the first dielectric layer (16) is then etched using a patterned masking layer (18)....
6207513 Spacer process to eliminate corner transistor device  
A method for forming spacers for preventing formation of parasitic corner devices in transistors includes etching trenches into a semiconductor substrate to form an active area region, lining the...
6204147 Method of manufacturing shallow trench isolation  
A method for manufacturing a shallow trench isolation. A substrate is provided, wherein the substrate has a pad oxide on the substrate and a silicon nitride layer on the pad oxide layer, and a...
6204131 Trench structure for isolating semiconductor elements and method for forming the same  
A trench structure for isolating semiconductor elements includes a trench formed in a semiconductor substrate; and an insulating layer formed on the semiconductor substrate which fills up the...
6204137 Method to form transistors and local interconnects using a silicon nitride dummy gate technique  
A new method of forming MOS transistors has been achieved. A pad oxide layer is grown. A silicon nitride layer is deposited. Trenches are etched for planned STI. A trench liner is grown inside of...
6197659 Divot free shallow trench isolation process  
An improved process of fabricating a shallow trench isolation structure is provided. A semiconductor substrate is provided and an insulating layer is formed over the substrate. A nitride masking...
6197661 Semiconductor device with trench isolation structure and fabrication method thereof  
A semiconductor device with the trench isolation structure is provided, in which the leakage current problem does not occur. This device is comprised ofa semiconductor substrate, an isolation...
6194271 Method for fabricating flash memory  
A method of fabricating a flash memory. A gate is formed on a provided substrate. A first doping process is performed. A patterned mask layer is formed over the substrate. A shallow trench...
6190999 Method for fabricating a shallow trench isolation structure  
A method for fabricating a shallow trench isolation (STI) structure includes a pad oxide layer and a hard masking layer are sequentially formed over a semiconductor substrate. A trench is formed in...
6187637 Method for increasing isolation ability using shallow trench  
A method for increasing isolation ability is disclosed. A shallow trench into semiconductor device is formed on a wafer. Therefore the wafer owns a semiconductor substrate and wherein a first gate...
6187648 Method of forming a device isolation region  
A method of forming a device isolation region includes the steps of: forming a first dielectric film and an oxidation-resistant deposition film successively on a semiconductor substrate; forming a...
6187651 Methods of forming trench isolation regions using preferred stress relieving layers and techniques to inhibit the occurrence of voids  
Methods of forming trench isolation regions include the steps of forming a trench in a semiconductor substrate and lining the trench with a first electrically insulating layer. A stress-relief...
6184566 Method and structure for isolating semiconductor devices after transistor formation  
A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes laterally displaced source/drain regions and channel regions. First...
6180459 Method for fabricating a flash memory with shallow trench isolation  
A method for fabricating a flash memory is provided. The method contains sequentially forming a tunnel oxide layer, a first polysilicon layer, and a silicon nitride layer on a semiconductor...
6180489 Formation of finely controlled shallow trench isolation for ULSI process  
A method for forming planarized shallow trench isolation is described. A nitride layer is deposited over the surface of a semiconductor substrate. A plurality of isolation trenches are etched...
6180491 Isolation structure and method  
An isolation structure is provided that includes a substrate (10), a refill material such as a refill oxide (22), a gate dielectric such as a gate oxide layer (24), and a gate conductor layer such...
6180515 Method of fabricating self-align contact window with silicon nitride side wall  
A gate oxide layer, a polysilicon layer are patterned on a substrate. Then, a thermal oxidation is carried out to form the first silicon dioxide layer on the surface of the polysilicon layer. Then,...
6180466 Isotropic assisted dual trench etch  
A shallow trench isolation structure having rounded corners is formed at edge-rounding oxidation temperatures employing a two-step trench etching technique. Isotropic etching is first performed,...
6177333 Method for making a trench isolation for semiconductor devices  
A method of fabricating an integrated circuit includes forming an isolation trench in a semiconductor substrate and partially filling the trench with a dielectric material so that at least the...
6177317 Method of making nonvolatile memory devices having reduced resistance diffusion regions  
A method is described for manufacturing nonvolatile memory devices having reduced resistance diffusion regions. One embodiment of the method includes forming a multilayer structure over a substrate...
6177332 Method of manufacturing shallow trench isolation  
A method is described for manufacturing a shallow trench isolation. The method comprises the steps of providing a substrate having a pad oxide layer, a mask layer and a trench, wherein the trench...
6171909 Method for forming a stacked gate  
A method for forming a stacked gate of a flash memory cell is described. A first dielectric layer, a conductive layer and a silicon nitride layer are sequentially formed over a substrate. A...
6171928 Method of fabricating shallow trench insolation  
A method of fabricating a shallow trench isolation (STI). The method forms a spin-on glass layer after removing a pad oxide layer in a STI process in order to fill a cavity formed in an oxide layer...
Matches 401 - 450 out of 638 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >