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6403415 Semiconductor device having a metal barrier layer for a dielectric material having a high dielectric constant and a method of manufacture thereof  
The present invention provides a semiconductor device that has a metal barrier layer for a dielectric material, which can be used in an integrated circuit, if so desired. The semiconductor device...
6399449 Semiconductor circuit using trench isolation and method of fabrication a trench isolator  
In order to isolate a plurality of MOS and bipolar devices provided on the same chip, a plurality of first and second trenches are provided on a semiconductor substrate. Each of the first trenches...
6391720 Process flow for a performance enhanced MOSFET with self-aligned, recessed channel  
A method for forming a self-aligned, recessed channel, MOSFET device that alleviates the problems due to short channel and hot carrier effects while reducing inter-electrode capacitance is...
6391739 Process of eliminating a shallow trench isolation divot  
A process of fabricating a shallow trench isolation structure includes the steps of: providing a substrate; forming a first insulating layer over the substrate; forming a nitride masking layer over...
6391729 Shallow trench isolation formation to eliminate poly stringer with controlled step height and corner rounding  
A method of fabricating an integrated circuit including multiple devices and isolation structures separating the multiple devices includes depositing a mask layer with a first thickness above a...
6391722 Method of making nonvolatile memory having high capacitive coupling ratio  
A method of making a nonvolatile memory device having a high capacitive coupling ratio with a self-aligned floating gate is disclosed. A tunnel dielectric layer, a first conductive layer, and a...
6387764 Trench isolation process to deposit a trench fill oxide prior to sidewall liner oxidation growth  
This invention relates generally to a method of trench isolation used in the fabrication of semiconductor devices, wafers and the like. More specifically, the present invention related to a method...
6388303 Semiconductor device and semiconductor device manufacture method  
There is disclosed a semiconductor device in which trenches are formed at predetermined intervals on a silicon substrate. In each trench, a first silicon oxide film is formed with the upper region...
6387776 Method for forming trench isolation regions  
A method for forming trench isolation regions in a semiconductor device reliably electrically isolates a device and enhances a device density. The method for forming trench isolation regions...
6383837 Method of manufacturing a multi-chip semiconductor device effective to improve alignment  
A plurality of chips each having two or more alignment holes for transmitting a laser beam are stacked. The laser beam is irradiated onto the uppermost or lowermost one of the stacked chips. A...
6383877 Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer  
A method of forming a T-shaped isolation layer, a method of forming an elevated salicide source/drain region using the same, and a semiconductor device having the T-shaped isolation layer are...
6380027 Dual tox trench dram structures and process using V-groove  
A structure and method for simultaneously forming array structures and support structures on a substrate comprises forming the array structures to have a V-groove, forming the support structures to...
6380063 Raised wall isolation device with spacer isolated contacts and the method of so forming  
A semiconductor device having borderless contacts thereby providing a device having a reduced overall size. In particular, the device includes a plurality of shallow trench isolations and a...
6376299 Capacitor for semiconductor memory device and method of manufacturing the same  
Disclosed are a capacitor for a semiconductor memory device and a method of manufacturing the same. According to the present invention, the method includes the steps of: forming a lower electrode...
6372602 Method of forming a shallow trench isolation structure in a semiconductor device  
The present invention provides a method of forming a shallow trench isolation structure in a substrate. The method comprises the steps of: forming an isolation silicon oxide film which comprises an...
6372584 Method for making raised source/drain regions using laser  
A low thermal budget method for making raised source/drain regions in a semiconductor device includes covering a silicon substrate and gate stacks with an amorphous silicon film, and then melting...
6365468 Method for forming doped p-type gate with anti-reflection layer  
A method for forming doped p-type gate is disclosed as the following description. The method includes that, firstly, a semiconductor substrate is provided. The semiconductor substrate is etched to...
6362074 Integrated circuit processing with improved gate electrode fabrication  
An integrated circuit is fabricated with a layer of polysilicon located on top of shallow trench regions. The polysilicon is patterned so that the trench features are not exposed during an etching...
6352897 Method of improving edge recess problem of shallow trench isolation  
A method for improving an edge recess of a shallow trench isolation (STI). A SiO x layer with gap-filling ability is formed to fill the edge recess at the top corner of the STI. A part of the SiO...
6350660 Process for forming a shallow trench isolation  
First of all, a semiconductor substrate that has a pad oxide layer thereon is provided. Then a nitride layer is formed on the pad oxide layer. Next, a photoresist layer is formed and defined on the...
6350655 Semiconductor device and a method of manufacturing the same  
In a semiconductor device of this invention, a first trench having a uniformly inclined surface at a predetermined angle is formed downward from the surface of a semiconductor substrate. A second...
6350661 Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts  
An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon...
6348394 Method and device for array threshold voltage control by trapped charge in trench isolation  
A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A...
6348395 Diamond as a polish-stop layer for chemical-mechanical planarization in a damascene process flow  
A method of using diamond or a diamond-like carbon layer as a polish-stop for patterning a metal level into an inter-level dielectric substrate using a damascene process flow. The diamond or...
6342431 Method for eliminating transfer gate sacrificial oxide  
A method of forming a semiconductor device, includes forming a layer of oxide on a semiconductor substrate, forming a layer of silicon nitride on the oxide layer, forming isolation regions in the...
6333218 Method of etching contacts with reduced oxide stress  
A method for manufacturing a semiconductor device forms a trench of a trench isolation region in a portion of a top surface of a semiconductor substrates. Oxide is deposited as a trench liner in...
6331469 Trench isolation structure, semiconductor device having the same, and trench isolation method  
A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the...
6329271 Self-aligned channel implantation  
A short channel insulated gate field effect transistor has within the semiconductor body that houses the transistor a buried layer of the same conductivity type as the body but of higher impurity...
6326283 Trench-diffusion corner rounding in a shallow-trench (STI) process  
An isolation structure on an integrated circuit is formed using a shallow trench isolation process. A layer of buffer oxide is formed on a substrate. A layer of nitride is formed on the layer of...
6323143 Method for making silicon nitride-oxide ultra-thin gate insulating layers for submicrometer field effect transistors  
A method for making an improved ultra-thin silicon nitride-oxide gate insulating layer for field effect transistors (FETs) is achieved. After forming a field oxide to electrically isolate device...
6323092 Method for forming a shallow trench isolation  
A method for forming a shallow trench isolation structure. A substrate having a pad oxide layer and a first mask layer is provided. The first mask layer is patterned to form a first opening, a...
6323112 Method of fabricating integrated circuits  
A method of fabricating integrated circuits. An oxide layer and a patterned dummy gate layer are formed on a substrate. The patterned dummy gate layer is used as an implantation mask in a first ion...
6323082 Process for making a DRAM cell with three-sided gate transfer  
A DRAM device and a process of manufacturing the device. The DRAM device includes a bit-line coupled to a signal storage node through a transfer device that is controlled by a word line. The...
6316815 Structure for isolating integrated circuits in semiconductor substrate and method for making it  
A trench isolation structure characterized by a dielectric stud filling and spanning a trench in a semiconductor substrate is suggested for isolating the integrated circuits fabricated in the...
6313008 Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon  
The invention describes three embodiments of methods for forming a balloon shaped STI trench. The first embodiment begins by forming a barrier layer over a substrate. An isolation opening is formed...
6309949 Semiconductor isolation process to minimize weak oxide problems  
A process for forming an isolation region while substantially eliminating weak oxide effects, comprising the steps of obtaining a semiconductor substrate patterned with a plurality of mesas with...
6306737 Method to reduce source-line resistance in flash memory with sti  
A method of forming a semiconductor component having a conductive line (24) that crosses a trench (72). The method involves forming steps (104) in the sidewalls of the trench (72) in a...
6303462 Process for physical isolation of regions of a substrate board  
Process for physical isolation of regions (110) of a substrate board (100) comprising the following steps: a) formation of trenches (106) in the substrate, delimiting regions of the substrate...
6303413 Method of forming a shallow and deep trench isolation (SDTI) suitable for silicon on insulator (SOI) substrates  
A method of forming a shallow-deep trench isolation (SDTI) is provided that includes the steps of forming a pair of deep trenches through a silicon on insulator (SOI) layer without substantially...
6297082 Method of fabricating a MOS transistor with local channel ion implantation regions  
A fabrication method for a metal oxide semiconductor (MOS) transistor involves forming gate oxide layers of different thicknesses on a core region and a input/output (I/O) region. After forming...
6294419 Structure and method for improved latch-up using dual depth STI with impurity implant  
A method and structure for improving the latch-up characteristic of semiconductor devices is provided. A dual depth STI is used to isolate the wells from each other. The trench has a first...
6294817 Source/drain-on insulator (S/DOI) field effect transistor using oxidized amorphous silicon and method of fabrication  
Source and drain regions of field effect transistors are fabricated with an electrically insulating layer formed thereunder so as to reduce junction capacitance between each and a semiconductor...
6291300 Manufacturing method of semiconductor devices  
An element isolation method of a semiconductor device comprises the steps of forming an oxide film on a semiconductor substrate; forming a nitride film on the oxide film; forming an isolation...
6287921 Method of performing threshold voltage adjustment for MOS transistors  
The invention discloses a method of forming threshold voltage adjustment for MOS transistors. At first, a first oxide layer and a nitride layer are formed on a silicon substrate in sequence. Next,...
6281082 Method to form MOS transistors with a common shallow trench isolation and interlevel dielectric gap fill  
A new method of forming MOS transistors in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided. A pad oxide layer is deposited. A silicon...
6281103 Method for fabricating gate semiconductor  
A method for fabricating floating gate semiconductor devices, such as flash EEPROMs, and flash EEPROM memory arrays, is provided. The method includes providing a semiconductor substrate and forming...
6281081 Method of preventing current leakage around a shallow trench isolation structure  
An ion implantation method useful for fabricating shallow trench isolation structureimplants phosphorus ions instead of arsenic ions into a substrate when the source/drain regions of an NMOS device...
6281093 Method to reduce trench cone formation in the fabrication of shallow trench isolations  
A new method of fabricating shallow trench isolations has been achieved. A silicon dioxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the...
6277697 Method to reduce inverse-narrow-width effect  
A method to reduce the inverse-narrow-line-effect is described in which an active region and an isolation region are defined on a substrate. A doped region is formed adjacent to the substrate...
6277707 Method of manufacturing semiconductor device having a recessed gate structure  
A method of forming a semiconductor device on a substrate including the steps of: forming a first recess in the substrate; depositing an insulator in the first recess so that an isolation region is...
Matches 351 - 400 out of 638 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >