Matches 301 - 350 out of 639 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >
Match Document Document Title
6576509 Semiconductor integrated circuit device and method of manufacturing the same  
In forming a plug 21 of a polycrystalline silicon film in a contact hole 19 to which a bit line BL is connected, the upper surface of the plug 21 is retracted downward from the upper edge of...
6570215 Nonvolatile memories with floating gate spacers, and methods of fabrication  
In a nonvolatile memory, a floating gate includes a portion of a conductive layer ( 150 ), and also includes conductive spacers ( 610 ). The spacers increase the capacitive coupling between the...
6566225 Formation method of shallow trench isolation  
The present invention provides a formation method of a trench structure comprising forming a pad oxide layer on a substrate. A first polysilicon layer is formed on the pad oxide layer and an oxide...
6566241 Method of forming metal contact in semiconductor device  
A method of forming metal contacts in a semiconductor device having an active metal contact region and a bit line contact region is provided. In the method, a contact pad is formed in the active...
6566207 Semiconductor device fabricating method  
A method of fabricating a semiconductor device in which a LOCOS profile characteristic is applied to a normal shallow trench isolation (STI) structure thereby lowering compressive stress that is...
6566206 Semiconductor structure having more usable substrate area and method for forming same  
A semiconductor structure includes a first substrate portion having a surface and a first active region disposed in the first substrate portion. An insulator region is disposed on the first...
6562697 Methods of implanting ions into different active areas to provide active areas having increased ion concentrations adjacent to isolation structures  
Active areas of integrated circuits can be formed by implanting first ions into a first active area of a substrate adjacent to an isolation structure in the substrate and between a source and a...
6562694 Method of manufacturing a semiconductor device comprising semiconductor elements formed in a toplayer of a silicon wafer situated on a buried insulating layer  
A method of manufacturing a semiconductor device including semiconductor elements having semiconductor zones ( 17, 18, 24, 44, 45 ) formed in a top layer ( 4 ) of a silicon wafer ( 1 ) situated on...
6555844 Semiconductor device with minimal short-channel effects and low bit-line resistance  
A transistor device that includes at least two transistors, each transistor including a source region, a drain region, and a shallow trench isolation formed between and contiguous with the source...
6555434 Nonvolatile memory device and manufacturing method thereof  
A nonvolatile memory device with a high coupling ratio is disclosed. The nonvolatile memory device includes a semiconductor substrate having shallow trench isolation (STI) formed therein and active...
6548372 Forming sidewall oxide layers for trench isolation  
A shallow trench isolated integrated circuit may be formed by creating an oxidation enhancing region at the corner between a semiconductor structure surface and the trench. This region may be...
6548374 Method for self-aligned shallow trench isolation and method of manufacturing non-volatile memory device comprising the same  
A method of self-aligned shallow trench isolation and a method of manufacturing a non-volatile memory using the same are disclosed. An oxide layer, a first conductive layer and a nitride layer are...
6544839 Semiconductor integrated circuit device and a method of manufacturing the same  
A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in...
6544861 Method for forming isolation trench  
A method for forming an isolation trench in a semiconductor substrate is provided. An isolation trench is formed in a semiconductor substrate using a trench etch mask pattern. Sidewall spacers are...
6541342 Method for fabricating element isolating film of semiconductor device, and structure of the same  
In the method for fabricating an element isolating film of a semiconductor device, a trench is formed in the semiconductor substrate, and a side wall spacer is formed at a side wall of the trench....
6537879 Process for manufacturing a non-volatile memory cell with a floating gate region autoaligned to the isolation and with a high coupling coefficient  
A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide...
6531365 Anti-spacer structure for self-aligned independent gate implantation  
A method for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided. The method of the present invention includes the steps of forming a...
6521515 Deeply doped source/drains for reduction of silicide/silicon interface roughness  
Metal silicides form low resistance contacts on semiconductor devices such as transistors. Rough interfaces are formed between metal silicide contacts, such as NiSi and the source/drain regions of...
6518114 Method of forming an insulating zone  
The invention relates to a method of forming an insulating zone ( 14 ) around an active zone ( 12 ) in a semiconductor substrate, which method includes the following steps: forming a groove around...
6514822 Method and system for reducing thinning of field isolation structures in a flash memory device  
A method and system for providing a Flash memory device is disclosed. The Flash memory device includes a core and a periphery. The method and system include providing the core for the Flash memory...
6509225 Semiconductor device and method of manufacturing the same  
A semiconductor device comprises a first MOSFET and a second MOSFET. The first MOSFET includes a first gate insulating film formed on a semiconductor substrate and having a relatively large...
6504219 Indium field implant for punchthrough protection in semiconductor devices  
Provided is a technique for forming an indium field implant at the bottom of an STI trench to strengthen the p-well under field oxide, but to not weaken the n-well under the field oxide. The...
6503804 Method of manufacturing a semiconductor device  
A method of manufacturing semiconductor device is provided which can minimize the thinning of a nitride layer in the planarization process and inhibit the peripheral area of the nitride layer from...
6503813 Method and structure for forming a trench in a semiconductor substrate  
A method and structure for forming a trench in a semiconductor substrate that includes a semiconductor material such as silicon. The method and structure may be used to form a deep trench or a...
6503803 Method of fabricating a semiconductor integrated circuit device for connecting semiconductor region and electrical wiring metal via titanium silicide layer  
Disclosed is a method of fabricating a semiconductor device including forming an insulating film on a silicon substrate; forming a contact hole in the insulating film; depositing a titanium film to...
6498382 Semiconductor configuration  
The invention relates to a semiconductor configuration in which electrodes are insulated by a gas-filled or evacuated cavity. The semiconductor configuration includes at least two rigid electrodes;...
6498064 Flash memory with conformal floating gate and the method of making the same  
A flash memory comprises a substrate having trenches formed therein. A tunneling oxide is formed on a surface of the substrate and adjacent to the trenches. A raised isolation fillers is formed in...
6486038 Method for and device having STI using partial etch trench bottom liner  
A method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of (a) providing a silicon-on-insulator semiconductor wafer having a silicon active...
6486035 Semiconductor device and method for fabricating the same  
Semiconductor device and method for fabricating the same, the device including a semiconductor substrate, a recessed channel region recessed below a surface of the semiconductor substrate, and a...
6472319 Method for manufacturing capacitor of semiconductor memory device by two-step thermal treatment  
A method for manufacturing a capacitor of a semiconductor memory device by a two-step thermal treatment is provided. A lower electrode is formed on a semiconductor substrate. A dielectric layer is...
6472274 MOSFET with self-aligned channel edge implant and method  
A MOSFET device and method, the method involves forming the MOSFET device by selectively doping bordering channel regions in the device such that, in operation, the threshold, or turn-on, voltage...
6472277 Method for fabricating a semiconductor device with an improved short channel effect  
A semiconductor device includes a semiconductor substrate having a trench in its surface, an insulating film in the trench, a doped conductive layer on the insulating film, a gate insulation film...
6465873 Semiconductor gettering structures  
The present invention relates to the formation of multiple gettering structures within a semiconductive substrate by ion implantation through recesses in the semiconductive substrate. A preferred...
6461935 Method of manufacturing trench-shaped isolator  
A semiconductor device having a trench-shaped isolator, adjacent to the semiconductor element region is formed having a width which is continuously decreased in the downward direction for relaxing...
6461932 Semiconductor trench isolation process that utilizes smoothening layer  
A trenched-isolated semiconductor structure is created by a process that entails forming a patterned trench ( 54 ) along an upper surface of a semiconductor body ( 40 ). A dielectric layer ( 56 )...
6455382 Multi-step method for forming sacrificial silicon oxide layer  
Within a method for forming a sacrificial silicon oxide layer, there is first provided a silicon semiconductor substrate. There is then thermally oxidized the silicon semiconductor substrate at a...
6455383 Methods of fabricating scaled MOSFETs  
The scaled MOSFETs having a conductive barrier-metal layer sandwiched between a metal layer or a thick silicide layer on the top and a first conductive gate layer at the bottom are disclosed by the...
6455381 Method of manufacturing a semiconductor device having a trench isolation structure  
A method of manufacturing a semiconductor devices includes the formation of a pad insulating film, a polysilicon film and a silicon nitride film on a semiconductor substrate. A trench portion is...
6451654 Process for fabricating self-aligned split gate flash memory  
The present invention provides a process for fabricating a self-aligned split gate flash memory. First, a patterned gate oxide layer, a first patterned polysilicon layer, and a first patterned mask...
6448606 Semiconductor with increased gate coupling coefficient  
A reduced device geometry semiconductor memory device is provided which has increased device efficiency because of an increased gate coupling coefficient. Shallow trench isolations are formed in a...
6444515 Method of fabricating a semiconductor device  
A hard mask insulating layer is formed on a gate electrode which is formed on a main surface of a silicon substrate with a gate insulating layer interposed. An SiN sidewall spacer is directly...
6436838 Method of patterning lead zirconium titanate and barium strontium titanate  
In an embodiment of the present invention, a method is provided of patterning PZT layers or BST layers. For example, a PZT layer or a BST layer is plasma etched through a...
6417047 Manufacturing method of a non-volatile semiconductor memory device having isolation regions  
A cell array region and a peripheral transistor region are provided. In the cell array region, a plurality of memory cell transistors are formed, and element regions of the memory cell transistors...
6417054 Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxide  
A method for a self aligned TX with elevated source/drain (S/D) regions on an insulated layer (oxide) by forming a trench along side the STI and filling the trench with oxide. STI regions are...
6413809 Method of manufacturing a non-volatile memory having an element isolation insulation film embedded in the trench  
A semiconductor device has a semiconductor substrate, an element isolation insulation film embedded in a trench formed in said semiconductor substrate in a state of protruding from a surface of...
6413826 Gate insulator process for nanometer MOSFETS  
Methods of manufacturing insulating materials and semiconductor devices incorporating films having high dielectric constants are disclosed, in which the high-dielectric constant material is...
6413836 Method of making isolation trench  
A method of making an isolation trench structure in a semiconductor substrate is disclosed. A first layer is formed on a semiconductor substrate. The first layer is subsequently patterned to form...
6410405 Method for forming a field oxide film on a semiconductor device including mask spacer and rounding edge  
The present invention provides a method for forming a field oxide film on a semiconductor device. In particular, the present invention provides a method for forming a field oxide film on a...
6406976 Semiconductor device and process for forming the same  
Semiconductor devices and processes for forming the same. The semiconductor device includes field isolation regions within trenches lying within a semiconductor device substrate. The trenches...
6403432 Hardmask for a salicide gate process with trench isolation  
A method for forming of a self-aligned polysilicon gate MOSFET with silicon oxide shallow trench isolation is described wherein a hardmask is used to etch the polysilicon gate electrode. The...
Matches 301 - 350 out of 639 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >