Matches 251 - 300 out of 639 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >
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6730555 Transistors having selectively doped channel regions  
An integrated semiconductor system is provided that is formed on a substrate 10 . A dual implant mask 26 is used to change the characteristics of semiconductor devices formed in regions of the...
6727150 Methods of forming trench isolation within a semiconductor substrate including, Tshaped trench with spacers  
A method of forming trench isolation within a semiconductor substrate includes forming a first isolation trench of a first open dimension within a semiconductor substrate. The first isolation...
6723662 Methods of forming gate oxide films in integrated circuit devices using wet or dry oxidization processes with reduced chloride  
Methods of forming gate oxide films in integrated circuit devices using wet or dry oxidization processes with a reduced amount of chloride are disclosed. A gate oxide film is formed on a substrate...
6716710 Using a first liner layer as a spacer in a semiconductor device  
A method of fabricating a semiconductor device. A first layer comprising a first material is deposited to a first thickness on a sidewall of a stacked gate. A second layer comprising a second...
6703270 Method of manufacturing a semiconductor device  
A method of manufacturing a semiconductor device comprises the steps of: forming a patterned masking layer ( 3 ) of insulating material at a surface ( 2 ) of a semiconductor body ( 1 ), etching...
6703287 Production method for shallow trench insulation  
An improved method for producing a semiconductor device in which overpolishing is prevented at a chemical mechanical polishing time to eliminate the influence of peripheries on the object part. A...
6699756 Four-transistor static-random-access-memory and forming method  
A method for forming four transistors static-random-access-memory. The method comprises the steps of: providing a substrate which at least comprises a cell region and periphery region, wherein the...
6689665 Method of forming an STI feature while avoiding or reducing divot formation  
A method for forming shallow trench isolation (STI) features to reduce or avoid divot formation at STI trench corners including providing a shallow trench isolation (STI) feature included in a...
6677224 Method of forming stacked gate for flash memories  
The method of the present invention includes the steps of forming doped regions in the semiconductor substrate. A pad oxide layer is formed on the semiconductor substrate. A masking layer is formed...
6667226 Method and system for integrating shallow trench and deep trench isolation structures in a semiconductor device  
A semiconductor device and a method for constructing a semiconductor device is disclosed. A deep trench isolation structure ( 108 ) is formed proximate a surface of a semiconductor substrate ( 106...
6660599 Semiconductor device having trench isolation layer and method for manufacturing the same  
A semiconductor device is formed by including the step of forming a polycrystalline silicon layer on a semiconductor substrate which includes a pad oxide. A trench is formed in the semiconductor...
6656806 SOI structure and method of producing same  
A Silicon On Insulator (SOI) structure and method of producing an SOI structure that can prevent a short circuit between a Local Inter-Connect (LIC) and a well in the SOI structure is disclosed....
6656807 Grooved planar DRAM transfer device using buried pocket  
A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion...
6656816 Method for manufacturing semiconductor device  
A method for manufacturing a semiconductor device enables the formation of a well optimized for a fine MOS transistor and a well formed deep with a relatively low concentration for a high voltage...
6656793 Method of forming a self-aligned floating gate in flash memory cell  
A method of forming a self-aligned floating gate in a flash memory cell. A capping layer is formed on a trench insulating film. An etching process is then performed to etch the trench insulating...
6656798 Gate processing method with reduced gate oxide corner and edge thinning  
Disclosed is a method of processing a semiconductor gate structure on a semiconductor wafer, the method comprising providing a semiconductor structure with an active device area capped with a pad...
6653201 Method for forming an isolation region in a semiconductor device  
A method for forming an isolation region in a semiconductor device, in which nitrogen ions are injected into a region of an isolation oxide film to form an oxynitride film, thereby preventing...
6653203 Thin sidewall multi-step HDP deposition method to achieve completely filled high aspect ratio trenches  
A multi-step HDP deposition and sputtering process for void-free filling of high aspect ratio trenches and for trenches having stepped cross-sectional profiles. The method is particularly...
6653194 Method for forming contact hole in semiconductor device  
Disclosed is a method for forming a contact hole in the process of manufacturing a logic device employing a shallow trench isolation (STI) method. The method prevents an isolation region from being...
6653204 Method of forming a shallow trench isolation structure  
A pad oxide layer and a silicon nitride (SiN) layer are sequentially formed on a silicon substrate. An etching process is then performed to form a trench in the silicon substrate. A sub-atmospheric...
6649489 Poly etching solution to improve silicon trench for low STI profile  
A method of etch polysilicon adjacent to a recessed STI structure feature is described. A substrate is provided with a dielectric layer thereon and a polysilicon layer on the dielectric layer. A...
6649481 Methods of fabricating a semiconductor device structure for manufacturing high-density and high-performance integrated-circuits  
The invention discloses methods of fabricating a semiconductor device structure having low source/drain junction capacitances and low junction leakage currents. The low source/drain junction...
6649461 Method of angle implant to improve transistor reverse narrow width effect  
A new angle implant is provided that reduces or eliminates the effects of narrow channel impurity diffusion to surrounding regions of insulation. The invention provides for angle implantation of...
6645825 Planarization of shallow trench isolation (STI)  
An improved and new process for fabricating a planarized structure of shallow trench isolation (STI) embedded in a silicon substrate has been developed. The planarizing method comprises a two-step...
6642109 Method of manufacturing a flash memory cell  
A method of manufacturing a flash memory cell in which an ion implantation process is performed before a cleaning process for etching a protrusion of a trench insulating film to a nipple shape. As...
6635551 Deep trench isolation for reducing soft errors in integrated circuits  
An integrated circuit having improved soft error protection and a method improving the soft error protection of an integrated circuit are disclosed. The integrated circuit comprises a substrate 72...
6635537 Method of fabricating gate oxide  
A method of fabricating a gate oxide layer. A mask layer isformed on a substrate. The mask layer and the substrate are patterned to form a trench in the substrate. A portion of the mask layer is...
6624016 Method of fabricating trench isolation structures with extended buffer spacers  
The trench-isolation structures for fabricating semiconductor devices using two different multilayer masking structures are disclosed by the present invention, in which the extended buffer spacers...
6620681 Semiconductor device having desired gate profile and method of making the same  
In a method of manufacturing a non-volatile memory or other semiconductor device, a control gate made of conductive material is formed in a more uniform fashion. The method includes forming a...
6617216 Quasi-damascene gate, self-aligned source/drain methods for fabricating devices  
Methods for use in fabricating integrated circuit structures. One embodiment of the present invention is a quasi-damascene gate, self-aligned source/drain method for forming a device on a substrate...
6617096 Method of producing an integrated circuit configuration  
A method of producing an integrated circuit configuration where trenches are formed surrounding active regions in a main surface of a semiconductor substrate. A photoresist layer is applied to the...
6613644 Method for forming a dielectric zone in a semiconductor substrate  
A method for forming a dielectric zone in a region of a semiconductor substrate is described. A first trench and a second trench are formed in the region of the semiconductor substrate resulting in...
6613646 Methods for reduced trench isolation step height  
Shallow trench isolation techniques are disclosed in which a thin nitride layer is formed on a semiconductor substrate, and a trench is formed through the nitride layer and into the semiconductor...
6610577 Self-aligned polysilicon polish  
A method for removing polysilicon from isolation regions on a substrate during semiconductor fabrication is disclosed. The method includes depositing a layer of polysilicon over the substrate, and...
6607959 Integrated circuit devices having trench isolation structures and methods of fabricating the same  
Integrated circuit devices include an integrated circuit substrate having a face and a trench in the face. The trench has a trench sidewall and a trench floor. A first insulating layer is provided...
6605506 Method of fabricating a scalable stacked-gate flash memory device and its high-density memory arrays  
A scalable stacked-gate flash memory device and its high-density memory arrays are disclosed by this invention. There are four different spacer techniques used to fabricate a scalable stacked-gate...
6605509 Method for forming smooth floating gate structure for flash memory  
A method for forming a smooth floating gate structure for a flash memory is disclosed. The method comprises the following steps. A substrate is firstly provided, and a first conductive layer and a...
6605512 Manufacturing method of a semiconductor device  
The invention provides a non-destructive inspection method for a selectively grown film and a manufacturing method of a semiconductor device for providing a simple and convenient process control...
6599789 Method of forming a field effect transistor  
A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides...
6599811 Semiconductor device having a shallow isolation trench  
A method for forming a semiconductor device having an isolation trench for separation of element regions includes the steps of forming a pad oxide film and a silicon nitride film on a silicon...
6596609 Method of fabricating a feature in an integrated circuit using two edge definition layers and a spacer  
A method of fabricating a feature on a substrate is disclosed. In a described embodiment the feature is the gate electrode of an MOS transistor. In this embodiment a polysilicon layer is formed on...
6596584 Method for fabricating a self-aligned source line flash memory device  
A method for fabricating a flash memory device having a self-aligned source includes providing a semiconductor substrate having a source region separated from a drain region by a channel region....
6596589 Method of manufacturing a high coupling ratio stacked gate flash memory with an HSG-SI layer  
A stacked-gate flash memory cell includes a trench formed in a substrate and a tunneling oxide layer formed on the substrate. A first part of the floating gate is formed on the tunneling oxide...
6596607 Method of forming a trench type isolation layer  
A method of forming a trench type isolation layer is provide, wherein the method comprises: forming a trench by etching after forming a trench etching pattern on a substrate; forming a silicon...
6586814 Etch resistant shallow trench isolation in a semiconductor wafer  
A shallow isolating trench is formed in a semiconductor wafer between active component areas to electrically isolate the active components from each other. The isolating trench is primarily formed...
6586295 Semiconductor device manufacturing method and semiconductor device  
A trench 5 for element separation is formed in a silicon substrate 1 by an etching process using an SiO 2 film 2 as a mask (FIG. 1 B). Side walls 18 are formed in a manner covering the...
6583025 Method of forming a trench isolation structure comprising annealing the oxidation barrier layer thereof in a furnace  
A method of forming a trench isolation structure prevents a nitride liner from being over-etched, i.e., prevents the so-called dent phenomenon from occurring. An etching mask pattern is formed on a...
6579767 Method for forming aluminum oxide as a gate dielectric  
A method for forming a gate structure begins by preparing a semiconductor substrate provided with an isolation region formed therein. A thin SiO 2 layer is thermally grown on top of the...
6579777 Method of forming local oxidation with sloped silicon recess  
A method of forming a localized oxidation having reduced bird's beak encroachment in a semiconductor device by providing an opening in the silicon substrate that has sloped sidewalls with a taper...
6576957 Etch-stopped SOI back-gate contact  
The buried oxide region has a layer added which etches selectively with respect to oxide, allowing the contacts to a gate or to a back gate to be created without overetching into the buried oxide...
Matches 251 - 300 out of 639 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >