Matches 601 - 641 out of 641 < 1 2 3 4 5 6 7 8 9 10 11 12 13
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5108946 Method of forming planar isolation regions  
A method of forming planar isolation regions in semiconductor structures includes providing a semiconductor substrate and forming a semiconductor layer thereon. A dielectric layer comprising at...
5093273 Method of manufacturing a semiconductor device  
A semiconductor device comprising three recessed portions formed at a very small pitch on the surface of a semiconductor substrate, remaining regions formed between these recessed portions as...
5087584 Process for fabricating a contactless floating gate memory array utilizing wordline trench vias  
A process for fabricating ultra-high density (e.g., 64Mbit) contactless EPROMs and/or flash EPROMs in a silicon substrate is described. Spaced-apart island members are formed of poly 2/...
5015601 Method of manufacturing a nonvolatile semiconductor device  
A source diffusion region and a drain diffusion region are formed under an insulation film which is thicker than a gate insulation film and which isolates the adjacent channel regions from each...
4981812 Process for fabricating a semiconductor read only memory  
In a process for fabricating a semiconductor read only memory, a gate oxidation film is grown on a semiconductor substrate, and a first polycrystalline silicon layer is then grown on the gate...
4973562 Method of manufacturing a semiconductor device having interconnections located both above a semiconductor region and above an isolation region adjoining it  
A method of manufacturing a semiconductor device, in which a first pattern of conductors (20), an isolating layer (21) and a second pattern of conductors (22) are successively provided on a surface...
4900693 Process for making polysilicon field plate with improved suppression of parasitic transistors  
A method of forming silicon integrated circuits offers radiation resistance together with a high degree of planarity, including a thin field oxide together with a set of conductive plates over the...
4892840 EPROM with increased floating gate/control gate coupling  
Disclosed is a floating gate memory array having high-speed programming capabilities. Diffused buried bit lines (14) are formed spaced apart in a semiconductor, forming conduction channels...
4874717 Semiconductor circuit containing integrated bipolar and MOS transistors on a chip and method of producing same  
Integrated semiconductor circuits with at least one bipolar transistor (17) and at least one MOS field effect transistor (18) on a chip wherein contacts from a metal interconnect level to diffused...
4830975 Method of manufacture a primos device  
A PRIMOS (Planar Recessed Isolated MOS) transistor and a method for fabricating same is described wherein the source and drain in a semiconductor body are separated by a recess. A gate oxide is...
4803173 Method of fabrication of semiconductor device having a planar configuration  
An MOS device having a planar configuration in which the top surfaces of the source, drain and gate electrodes are coplanar, and the overlying electrical contact structure is also planar, is...
4764483 Method for burying a step in a semiconductor substrate  
Disclosed is a method for burying a step in a semiconductor substrate in which (1) SiO 2 layer is formed on a lower part of the step, (2) photoresist layer with equal thickness to the height of...
4755478 Method of forming metal-strapped polysilicon gate electrode for FET device  
A process for forming a planarized, low sheet resistance FET. A gate stack is defined on an exposed surface of a semiconductor substrate, the gate stack including a gate mask disposed on a...
4753897 Method for providing contact separation in silicided devices using false gate  
A method for providing platinum or tungsten silicide contacts to source, drain, gate and tub regions of a dielectrically isolated MOSFET is described. A "false" (dummy) gate is used to provide...
4737828 Method for gate electrode fabrication and symmetrical and non-symmetrical self-aligned inlay transistors made therefrom  
An edge defining method is employed in the fabrication of narrow electrical patterns for VLSI circuits. The method is particularly employable in the formation of inlay MOSFET transistors having...
4727048 Process for making isolated semiconductor structure  
An integrated circuit structure comprises a plurality of islands of semiconductor material (16-1 through 16-5) each island being separated from adjacent islands by a groove formed in annular shape...
4700464 Method of forming trench isolation in an integrated circuit  
A semiconductor integrated circuit device is provided with polycrystalline silicon filling U-grooves etched in a semiconductor substrate to form isolation regions which prevent any short-circuiting...
4698900 Method of making a non-volatile memory having dielectric filled trenches  
A cross point EPROM array has trenches to provide improved isolation between adjacent buried N+ bitlines at locations where the adjacent buried N+ bitlines are not separated by a FAMOS transistor....
4688314 Method of making a planar MOS device in polysilicon  
A highly planarized integrated circuit structure having at least one MOS device is described as well as a method of making the structure. The structure comprises a substrate having a field oxide...
4683637 Forming depthwise isolation by selective oxygen/nitrogen deep implant and reaction annealing  
MOS transistors in which the source and drain contact are isolated from the common substrate are formed by using the gate conductor to mask a high dose high energy implant which creates a thin...
4677736 Self-aligned inlay transistor with or without source and drain self-aligned metallization extensions  
A self-aligned process is described for depositing gate electrode material in an inlay field effect transistor. The process particularly provides means for inclusion of lightly doped source and...
4651411 Method of manufacturing a MOS device wherein an insulating film is deposited in a field region  
A method of manufacturing a MOS device wherein a semiconductor substrate is selectively etched to form a groove in a field region and an element formation region surrounded by the groove such that...
4630343 Product for making isolated semiconductor structure  
An integrated circuit structure comprises a plurality of islands of semiconductor material (16-1 through 16-5) each island being separated from adjacent islands by a groove formed in annular shape...
4596071 Method of making semiconductor devices having dielectric isolation regions  
A method of making semiconductor devices having fine dielectric element isolation regions is disclosed. The method comprises the steps of preparing a semiconductor substrate of one conductivity...
4566940 Manufacturing process for semiconductor integrated circuits  
A semiconductor integrated circuit in which layers such as an field isolation region, a gate electrode, interlayer insulating films and interconnection lines are formed by the combined use of a...
4539782 Silo for loose material in powder form  
A silo for loose material in powder form having a base provided with a central conical section projecting upwards to form an annular discharge zone having floor portions inclined in a direction...
4532696 Method of manufacturing a semiconductor device for forming a deep field region in a semiconductor substrate  
This invention provides a method of forming a buried element isolation region in a semiconductor substrate. The method comprises steps of forming a gate electrode material pattern on a gate...
4529456 Method of forming bifets by forming isolation regions connected by diffusion in semiconductor substrate and epitaxial layer  
The present invention relates to a method of manufacturing a semiconductor integrated circuit device, especially a Bi-MOS IC. It comprises: 1. introducing an impurity of a first conductivity...
4507849 Method of making isolation grooves by over-filling with polycrystalline silicon having a difference in impurity concentration inside the grooves followed by etching off the overfill based upon this difference  
A groove having a semiconductor layer buried therein is formed on one main surface of a semiconductor substrate, said groove providing a region for separating adjacent semiconductor elements. In...
4506434 Method for production of semiconductor devices  
A method for producing semiconductor devices having a substrate, element fabrication areas formed in the substrate and isolation areas surrounding the element fabrication areas. The method...
4506435 Method for forming recessed isolated regions  
A method is described for forming the recessed dielectric isolation in a silicon substrate involves first forming trenches which may be less than about 1 micron in depth in areas of one principal...
4504333 Method of making field oxide regions  
A semiconductor device wherein an oxide film constituting a field region is buried in a semiconductor substrate to make the surface of the field region flush with the top surface of an element...
4497108 Method for manufacturing semiconductor device by controlling thickness of insulating film at peripheral portion of element formation region  
A method of manufacturing a semiconductor device wherein a thickness of an insulating film at a peripheral portion of an element formation region of a semiconductor substrate is increased. The...
4486266 Integrated circuit method  
A CMOS integrated circuit made up of complementary insulated gate field effect transistors incorporates isolation trenches formed by a combination of thermal growth of silicon dioxide and chemical...
4424621 Method to fabricate stud structure for self-aligned metallization  
A self-aligned metal process is described which achieves self-aligned metal silicon contacts and micron-to-submicron contact-to-contact and metal-to-metal spacing by use of the pattern of...
4404735 Method for manufacturing a field isolation structure for a semiconductor device  
A method for forming a field isolation structure for a semiconductor device, in which a groove is formed in a semiconductor substrate, an insulating layer is formed on the substrate at least in the...
4394196 Method of etching, refilling and etching dielectric grooves for isolating micron size device regions  
A method for manufacturing a semiconductor device comprising: (a) a step of forming at least one groove(s) at the predetermined portion(s) of a semiconductor substrate; (b) a step of depositing...
4274909 Method for forming ultra fine deep dielectric isolation  
A method is shown for forming ultra fine, deep dielectric isolation in a silicon body. The method involves forming a first layer of material on the silicon body over a first set of alternately...
4252579 Method for making single electrode U-MOSFET random access memory utilizing reactive ion etching and polycrystalline deposition  
A method for making highly dense, dielectrically isolated, U-shaped MOSFET. In a preferred method a monocrystalline silicon P substrate with a N+ layer thereon, a P layer on the N+ layer and a N+...
4234362 Method for forming an insulator between layers of conductive material  
A method for forming an insulator between conductive layers, such as highly doped polycrystalline silicon, that involves first forming a conductive layer of, for example, polycrystalline silicon on...
3869786 Semiconductor component and its method of manufacturing  
This invention relates to a MOS semiconductor device having a mesa-shaped projection concentrically surrounded by a field plane electrode processed in a self-aligning etching method upon an...
Matches 601 - 641 out of 641 < 1 2 3 4 5 6 7 8 9 10 11 12 13