Matches 551 - 600 out of 641 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >
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5858830 Method of making dual isolation regions for logic and embedded memory devices  
A method for forming thick field oxide regions, to be used for isolation in MOSFET memory regions, while also forming insulator filled, narrow trenches, to be used for isolation purposes in MOSFET...
5854112 Transistor isolation process  
In the manufacture of semiconductor devices on a single substrate, said devices comprising a source region, a drain region and a gate therebetween, forming an isolation region after formation of...
5851881 Method of making monos flash memory for multi-level logic  
The present invention provides a structure and method of manufacturing split gate MONOS multi-level logic memory device. The memory device has a poly stacked gate transistor 20A in series with a...
5843824 Diode-based semiconductor read-only memory device and method of fabricating the same  
A diode-based ROM device and a method for fabricating the same are provided. The ROM device is of the type including an array of diode-based memory cells for permanent storage of binary-coded data...
5837612 Silicon chemical mechanical polish etch (CMP) stop for reduced trench fill erosion and method for formation  
A method for forming shallow trench isolation (STI) (100) begins by forming an oxidizable layer (106) preferably made of polysilicon. An opening is patterned and etched through this layer (106) to...
5830797 Interconnect methods and apparatus  
A damascene method of forming planarized interconnects between conductive material layers in trench-isolated cells in an integrated circuit is disclosed. The method includes depositing and...
5830796 Method of manufacturing a semiconductor device using trench isolation  
The present invention discloses a method of manufacturing a semiconductor device, comprising the steps of: forming a transistor on a silicon substrate; forming a trench by etching a selected...
5811347 Nitrogenated trench liner for improved shallow trench isolation  
A method of forming an improved isolation trench between active regions within the semiconductor substrate. The improved method incorporates a trench liner having a nitrogen content of...
5804862 Semiconductor device having contact hole open to impurity region coplanar with buried isolating region  
A MIS type field effect transistor has a source/drain region overlain by a titanium silicide layer contiguous to an upper silicon nitride layer of a buried isolating structure embedded into a...
5786262 Self-planarized gapfilling for shallow trench isolation  
A new method is disclosed to form a shallow trench isolation with a ozone-TEOS as a gapfilling material. The formation of the shallow trench isolation described herein includes a pad layer, a...
5780346 N.sub.2 O nitrided-oxide trench sidewalls and method of making isolation structure  
A method of forming an isolation structure in a semiconductor substrate is described. A trench is first etched into a semiconductor substrate. A first oxide layer is then formed with the trench....
5770504 Method for increasing latch-up immunity in CMOS devices  
The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by reducing the...
5770501 Process of fabricating NAND-structure flash EEPROM using liquid phase deposition  
A process of fabricating a flash EEPROM having a NAND structure by using the liquid phase deposition (LPD) technique and self-alignment technique is disclosed to achieve higher density and...
5766971 Oxide strip that improves planarity  
A process for stripping thin layers of oxide such as sacrificial pad oxide employs etching chemistry that widens cracks to remove shallow cracks and limit the widening of deep cracks, thereby...
5763309 Self-aligned isolation and planarization process for memory array  
A self-aligned planarization and isolation technique achieves smaller dimension memory cells using self-aligned isolation trenches. The process involves defining the lines of buried diffusion and...
5753961 Trench isolation structures for a semiconductor device  
A semiconductor device includes a body of semiconductor material having first trenches and second trenches. Each of the first trenches has vertical sidewalls and each of the second trenches has...
5753562 Methods of forming semiconductor devices in substrates having inverted-trench isolation regions therein  
Methods of forming semiconductor substrates having inverted-trench isolation regions therein include the steps of forming at least one trench in a semiconductor substrate at a first face thereof...
5741738 Method of making corner protected shallow trench field effect transistor  
A semiconductor structure to prevent gate wrap-around and corner parasitic leakage comprising a semiconductor substrate having a planar surface. A trench is located in the substrate, the trench...
5731237 Method of producing an EPROM with a trench insulating layer  
An EPROM allowing a miniaturization of an isolation region (a field insulating layer) without generating a parasitic transistor. The EPROM comprises a semiconductor substrate; a field insulating...
5731239 Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance  
A method for making low sheet resistance sub-quarter-micrometer gate electrode lengths on field effect transistors has been achieved. The method involves patterning gate electrodes on a silicon...
5731241 Self-aligned sacrificial oxide for shallow trench isolation  
The present invention provides a method of manufacturing a sacrificial self aligned sub-atmospheric chemical vapor deposition (SACVD) O 3 TEOS layer 50 70 over a trench oxide 40 to protect the...
5728621 Method for shallow trench isolation  
A new method for forming planarized high quality oxide shallow trench isolation is described. A nitride layer overlying a pad oxide layer is provided over the surface of a semiconductor substrate....
5728620 Isolation method of semiconductor device  
A device isolation method divides a semiconductor substrate into active and inactive regions. A first device isolation layer is formed in a first inactive region using a trench isolation method....
5726084 Method for forming integrated circuit structure  
A integrated circuit structure and a method of fabrication thereof are provided. In particular, fully planarized, trench isolated semiconductor regions, e.g. comprising doped polysilicon, are...
5721173 Method of forming a shallow trench isolation structure  
A method of forming a trench isolation structure is provided in which a film is formed on a semiconductor substrate and a trench is formed in the semiconductor substrate through the film. A...
5719085 Shallow trench isolation technique  
A method of forming a trench isolation region. The method of the present invention comprises the steps of forming an opening in a semiconductor substrate, oxidizing the opening a first time, and...
5693542 Method for forming a transistor with a trench  
A method for forming a transistor comprising the steps of: forming a trench in a substrate; filling an insulating layer in the lower portion of said trench except for the upper portion thereof;...
5679591 Method of making raised-bitline contactless trenched flash memory cell  
A raised-bitline, contactless flash memory device with trenches on a semiconductor substrate doped with a first conductivity type includes a first well of an opposite conductivity type comprising a...
5674775 Isolation trench with a rounded top edge using an etch buffer layer  
The present invention provides a method of manufacturing a trench having rounded top corners 28 in a substrate. The rounded top edges allow the formation of a gate oxide with a uniform thickness...
5672530 Method of making MOS transistor with controlled shallow source/drain junction  
The invention provides an improved technique for forming a MOS transistor having lightly doped source and drain junction regions and low parasitic capacitance. The transistor includes raised source...
5624866 Semiconductor device provided with trench element isolation film and method for fabricating the same  
A semiconductor device with a trench element isolation structure having a trench element isolation film formed to have a small width at the boundary between an active region and a field region,...
5614430 Anti-punchthrough ion implantation for sub-half micron channel length MOSFET devices  
A method for forming a MOSFET device, with reduced exposure to source and drain leakage currents, that can arise due to a junction depletion punchthrough phenomena, has been developed. An...
5604159 Method of making a contact structure  
The horizontal surface area required to contact semiconductor devices, in integrated circuits fabricated with trench isolation, is minimized without degrading contact resistance by utilizing the...
5571738 Method of making poly LDD self-aligned channel transistors  
Short channel MOS devices are provided with two distinct doped polysilicon contacts: (a) doped polysilicon layers in contact with the source or drain regions (the LDD regions) and extending...
5561078 Method of fabrication of semiconductor device  
A method of fabricating a semiconductor device incorporates the steps of forming in succession a gate insulting film, a polycrystalline silicon film and a first insulating film on a semiconductor...
5529943 Method of making buried bit line ROM with low bit line resistance  
A ROM array comprises orthogal sets of buried bit lines and polysilicon wordlines. The buried bit lines comprise trenches with insulating material on the side walls, the trenches then being filled...
5506160 Method of fabricating a self-aligned trench isolation scheme for select transistors in an alternate metal virtual ground (AMG) EPROM array  
The present invention provides a self-aligned trench isolation scheme for the MOS select transistors in an alternate metal virtual ground (AMG) EPROM array architecture. The new isolation scheme...
5436190 Method for fabricating semiconductor device isolation using double oxide spacers  
A method for fabricating a very narrow electrical isolation trench in a semiconductor substrate for isolating the individual field effect transistors (FETs) is achieved. This method eliminates the...
5387534 Method of forming an array of non-volatile sonos memory cells and array of non-violatile sonos memory cells  
An array of SONOS memory cells includes: a) a pair of spaced, adjacent SONOS gates atop a silicon substrate within an array area; b) a trench between the gates, the trench having opposing...
5380671 Method of making non-trenched buried contact for VLSI devices  
The invention describes a non-trenched buried contact for local interconnections in VLSI devices and provides a method for forming the non-trenched buried contact. By using trenched isolation and a...
5366911 VLSI process with global planarization  
A method of fabricating an integrated circuit which maintains global planarization throughout the process flow is achieved. Trenched isolation regions are formed within a silicon substrate....
5342480 Method of manufacturing a semiconductor integrated circuit device  
An isolation and flattening technique for a semiconductor substrate having active devices, such as a bipolar transistor, and a MISFET, formed thereon, is disclosed. The technique includes forming...
5340769 Method for manufacturing semiconductor device having groove-structured isolation  
A conductive layer is formed on a semiconductor substrate, and is etched so that a side face of the conductive layer is reversely-tapered. Also, a sidewall insulating layer is formed on the side...
5292683 Method of isolating semiconductor devices and arrays of memory integrated circuitry  
A semiconductor processing device isolation method includes: a) providing non-LOCOS insulating device isolation blocks by trench and refill technique on a substrate to define recessed moat volume...
5254491 Method of making a semiconductor device having improved frequency response  
A technique for improving the frequency response of a semiconductor device employing silicon as the semiconductor material. Parasitic components inherent in semiconductor devices degrade the...
5238870 Exposure process for writing a pattern on an object  
A method for exposing a surface of an object to a radiation beam for writing a pattern thereon. The method includes the steps of producing a radiation, shaping the radiation to form a shaped...
5225358 Method of forming late isolation with polishing  
Isolation and passivation structures are formed in a single step, after transistor fabrication, by CVD deposition of a layer of oxide or BPSG over the wafer. The passivation/isolation layer...
5202286 Method of forming three-dimensional features on substrates with adjacent insulating films  
A method of producing a three-dimensional feature on a substrate and adjacent electrically insulating films comprising producing a resist on a portion of a surface of a substrate; etching the...
5177028 Trench isolation method having a double polysilicon gate formed on mesas  
A method of forming isolation trenches and mesa areas in a semiconductor substrate and of forming FETs in the mesa areas is disclosed. The method includes providing a first oxide layer, a first...
5173436 Method of manufacturing an EEPROM with trench-isolated bitlines  
An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using a floating-gate transistor with or without a split gate. The floating-gate transistor may have a...
Matches 551 - 600 out of 641 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >