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7598146 Self-aligned gate and method  
A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated...
7534708 Recessed-type field effect transistor with reduced body effect  
For fabricating a field effect transistor, an extra-doped channel region is formed below a surface of a semiconductor substrate. An opening is formed in the semiconductor substrate into the...
7514318 Method for fabricating non-volatile memory cells  
A method for fabricating non-volatile memory cells is provided. The method includes providing a substrate, forming a first dopant region in the substrate, forming a second dopant region in the...
7504309 Pre-silicide spacer removal  
A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in...
7501325 Method for fabricating semiconductor device  
The method for fabricating the semiconductor device comprises: the step of forming a ferroelectric capacitor over a semiconductor substrate 10 ; the step of forming an insulating film 54 ,...
7494872 Field effect transistor having a doped gate electrode with reduced gate depletion and method of forming the transistor  
By forming an implantation mask prior to the definition of the drain and the source areas, an effective decoupling of the gate dopant concentration from that of the drain and source concentrations...
7491605 Zero cost non-volatile memory cell with write and erase features  
A method for making a semiconductor structure of a memory device includes forming a capacitor having a gate dielectric between a gate conductor and a dopant region of a first conductivity type...
7427546 Transistor device and method for manufacturing the same  
A transistor device includes a recess in a surface of semiconductor substrate, a gate insulation layer formed over an inner side of the recess, a gate conductor filling the recess in which the gate...
7393767 Method for implanting a cell channel ion of semiconductor device  
A method for implanting a cell channel ion of semiconductor device is disclosed. In accordance with the method, the bit line contact region and the edge portion of the channel region adjacent to...
7381621 Methods of fabricating high voltage MOSFET having doped buried layer  
A MOSFET includes an insulated gate electrode on a surface of a semiconductor substrate having an impurity region of first conductivity type therein that extends to the surface. Source and drain...
7344947 Methods of performance improvement of HVMOS devices  
Methods fabricate DEMOS devices having varied channel lengths and substantially similar threshold voltages. A threshold voltage is selected for first and second devices. First and second well...
7288445 Double gated transistor and method of fabrication  
Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the...
7279388 Method for manufacturing transistor in semiconductor device  
Disclosed is a method for manufacturing a transistor in a semiconductor device, which can improve a device's refresh characteristics. The method includes: providing a silicon substrate having...
7259054 Method of manufacturing a semiconductor device that includes a process for forming a high breakdown voltage field effect transistor  
With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n + type semiconductor regions,...
7247541 Method of manufacturing a semiconductor memory device including a transistor  
A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate...
7217624 Non-volatile memory device with conductive sidewall spacer and method for fabricating the same  
The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate...
7208385 LDMOS transistor with enhanced termination region for high breakdown voltage with on-resistance  
A structure for making a LDMOS transistor ( 100 ) includes an interdigitated source finger ( 26 ) and a drain finger ( 21 ) on a substrate ( 15 ). Termination regions ( 35, 37 ) are formed at the...
7195967 Nonvolatile semiconductor memory device and manufacturing method thereof  
In a channel region between the source/drain diffusion layers, impurities of the same conductivity type as the well are doped in an area apart from the diffusion regions. By using as a mask the...
7192836 Method and system for providing halo implant to a semiconductor device with minimal impact to the junction capacitance  
A method and system for providing a halo implant to a semiconductor device is disclosed. The method and system includes providing a thin photoresist layer that covers a substantial amount of an...
7179714 Method of fabricating MOS transistor having fully silicided gate  
There is provided a method of fabricating a MOS transistor having a fully silicided gate, including forming a gate pattern and gate spacers on a semiconductor substrate, the gate pattern including...
7176538 High voltage MOSFET having doped buried layer  
A MOSFET includes an insulated gate electrode on a surface of a semiconductor substrate having an impurity region of first conductivity type therein that extends to the surface. Source and drain...
7141477 Semiconductor device and method for fabricating the same  
Into a channel formation region of a semiconductor substrate of p-type silicon, indium ions are implanted at an implantation energy of about 70 keV and a dose of about 5×10 13 /cm 2 , thereby...
7091093 Method for fabricating a semiconductor device having a pocket dopant diffused layer  
A gate electrode is formed over a semiconductor region with a gate insulating film interposed therebetween. An extended high-concentration dopant diffused layer of a first conductivity type is...
7081416 Methods of forming field effect transistor gates  
The invention includes methods of forming field effect transistor gates. In one implementation, a series of layers is formed proximate a semiconductive material channel region. The layers comprise...
7060572 MOSFET with short channel structure and formation method thereof  
A MOSFET with a short channel structure and manufacturing processes for the same are described. The MOSFET has a substrate, a channel region, a source/drain region, a gate dielectric layer and a...
7053450 Semiconductor device and method for fabricating the same  
A MISFET in a semiconductor device has a gate insulating film provided on a substrate, a gate electrode provided on the gate insulating film, sidewalls provided on the side surfaces of the gate...
7033894 Method for modulating flatband voltage of devices having high-k gate dielectrics by post-deposition annealing  
A method for modulating the flatband voltage of semiconductor devices includes post-deposition annealing of a high-k dielectric film deposited by chemical vapor deposition, for example. The...
7012006 Embedded ROM device using substrate leakage  
A ROM embedded DRAM provides ROM cells that can be programmed to a single state. The ROM cells include capacitors having a storage node. The storage node is processed to have a substantially high...
6987049 Semiconductor transistors and methods of fabricating the same  
In an example method for fabricating a transistor in a semiconductor device, a buffer insulation layer and a first insulation layer are deposited and etched, and poly electrodes for an LDD are...
6972234 High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage  
A method of fabricating CMOS devices suitable for high voltage and low voltage applications, while maintaining minimum channel lengths for the devices. In one embodiment, pocket implants ( 310 )...
6951793 Low-temperature polysilicon thin film transistor having buried LDD structure and process for producing same  
A low-temperature polysilicon thin film transistor having a buried LDD structure is provided. Two heavily doped regions are formed in a semiconductor layer and distributed just below a surface of...
6936517 Method for fabricating transistor of semiconductor device  
A method of fabricating a transistor of a semiconductor device is disclosed. The method of fabricating a transistor comprises forming a sacrificial layer on a substrate; forming a source/drain...
6930004 Self-aligned drain/channel junction in vertical pass transistor DRAM cell design for device scaling  
A method of formation of a deep trench vertical transistor is provided. A deep trench with a sidewall in a doped semiconductor substrate is formed. The semiconductor substrate includes a...
6905932 Method for constructing a metal oxide semiconductor field effect transistor  
A semiconductor device ( 100 ) and a method for constructing a semiconductor device ( 100 ) are disclosed. A trench isolation structure ( 112 ) and an active region ( 110 ) are formed proximate an...
6893921 Nonvolatile memories with a floating gate having an upward protrusion  
In a nonvolatile memory cell, the floating gate ( 160 ) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate ( 140 ). The spacer can be formed...
6884686 Method of manufacturing and structure of semiconductor device with floating ring structure  
A high voltage semiconductor device includes a drain region disposed within a semiconductor substrate. The semiconductor device further includes a field oxide layer disposed outwardly from the...
6881634 Buried-channel transistor with reduced leakage current  
In one embodiment, a buried-channel transistor is fabricated by masking a portion of an active region adjacent to a trench and implanting a dopant in an exposed portion of the active region to...
6879007 Low volt/high volt transistor  
A semiconductor device has at least one high-voltage and low-voltage transistor on a single substrate. The reliability of the high-voltage transistor is enhanced by performing a LDD implantation in...
6873008 Asymmetrical devices for short gate length performance with disposable sidewall  
An asymmetrical channel implant from source to drain improves short channel characteristics. The implant provides a relatively high V T net dopant adjacent to the source region and a relatively...
6852599 Method for fabricating MOS transistors  
A method for fabricating a metal oxide semiconductor (MOS) transistor, which can reduce the junction capacitance without degradation of transistor characteristics including forming a buffer oxide...
6838347 Method for reducing line edge roughness of oxide material using chemical oxide removal  
A method for reducing line edge roughness (LER) of a semiconductor gate structure includes patterning a photoresist layer formed over an oxide hardmask layer. The photoresist layer is etched so as...
6800511 Method for fabricating semiconductor device with negative differential conductance or transconductance  
The present invention relates to a method for fabricating semiconductor device with negative differential conductance or transconductance. According to the present invention, a fabrication process...
6790756 Self aligned channel implant, elevated S/D process by gate electrode damascene  
A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this...
6790754 Methods for manufacturing a semiconductor device  
Method for forming contact electrodes in a semiconductor device are disclosed. An example method comprises sequentially forming a pad oxide layer, a pad nitrate layer, a dummy oxide layer, and a...
6780698 Semiconductor device and its production method  
A method for producing a semiconductor device which comprises causing a dopant present in a semiconductor substrate to segregate in the surface of said semiconductor substrate, thereby forming a...
6746926 MOS transistor with highly localized super halo implant  
A method for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves a highly localized halo implant formed in the channel region but not in...
6743682 Method of manufacturing a semiconductor device  
In a method of manufacturing a semiconductor device comprising a semiconductor body 1 which is provided at a surface 2 with a transistor comprising a gate structure 21, a patterned layer 10 ...
6740556 Method for forming EPROM with low leakage  
A method for forming an electrically programmable read-only memory(EPROM) includes forming a first p + doped region, a second p + doped region, and a third p + doped region on an N-well, forming...
6727131 System and method for addressing junction capacitances in semiconductor devices  
A method of forming a semiconductor device is provided that comprises forming a gate conductor proximate to and insulated from an outer surface of a semiconductor substrate. The gate conductor...
6689662 Method of forming a high voltage power MOSFET having low on-resistance  
A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body...
Matches 1 - 50 out of 328 1 2 3 4 5 6 7 >