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7622353 Method for forming recessed gate structure with stepped profile  
Disclosed herein are a recess-gate structure in which junctions have a thickness significantly smaller than the thickness of a device isolation layer to thereby prevent shorting of the junctions...
7622351 Method of manufacturing semiconductor device and semiconductor device  
A method of manufacturing a semiconductor device, includes: forming a first and a second trench regions adjacent from each other in a first conductivity type semiconductor base; forming a second...
7618866 Structure and method to form multilayer embedded stressors  
A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is...
7615492 Preparing method of CNT-based semiconductor sensitized solar cell  
A solar cell is prepared. The solar cell is photo-sensitized. The solar cell has a semiconductor layer. And carbon nanotubes are deposited on the semiconductor layer with an arrangement. The solar...
7605041 Semiconductor device and its manufacture method  
Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second...
7601598 Reverse metal process for creating a metal silicide transistor gate structure  
The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate...
7598146 Self-aligned gate and method  
A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated...
7595243 Fabrication of semiconductor structure having N-channel channel-junction field-effect transistor  
A semiconductor technology combines a normally off n-channel channel-junction insulated-gate field-effect transistor (“IGFET”) ( 104 ) and an n-channel surface-channel IGFET ( 100 or 160 ) to...
7588986 Method of manufacturing a semiconductor device  
According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device having active regions including a SONOS device region, a high voltage device region,...
7582534 Chemical doping of nano-components  
A method is provided for doping nano-components, including nanotubes, nanocrystals and nanowires, by exposing the nano-components to an organic amine-containing dopant. A method is also provided...
7569449 Processes providing high and low threshold p-type and n-type transistors  
Methods of fabricating negative-channel metal-oxide semiconductor (NMOS) devices and positive-channel metal-oxide semiconductor (PMOS) devices having complementary threshold voltages are described....
7569444 Transistor and method for manufacturing thereof  
A transistor includes a gate insulating layer over a semiconductor substrate; a first insulating layer on both sides of the gate insulating layer; first spacers over the first insulating layer and...
7566934 Semiconductor device to suppress leak current at an end of an isolation film  
A semiconductor device is formed on an SOI substrate having a silicon layer formed on an insulating layer. A transistor element is formed in the silicon layer of the SOI substrate. An isolation...
7563682 LDMOS transistor device, integrated circuit, and fabrication method thereof  
An LDMOS transistor device in an integrated circuit comprises a semiconductor substrate ( 10 ), a gate region ( 1 ) including a gate semiconductor layer region ( 2; 2′; 151 ) on top of a gate...
7557023 Implantation of gate regions in semiconductor device fabrication  
A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and...
7550354 Nanoelectromechanical transistors and methods of forming same  
Nanoelectromechanical transistors (NEMTs) and methods of forming the same are disclosed. In one embodiment, an NEMT may include a substrate including a gate, a source region and a drain region; an...
7544595 Forming a semiconductor device having a metal electrode and structure thereof  
A method for forming a semiconductor device includes forming a gate dielectric over a substrate, forming a metal electrode over the gate dielectric, forming a first sacrificial layer which includes...
7531404 Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer  
A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal...
7524728 Thin film transistor manufacturing method and organic electroluminescent display device  
The invention reduces display unevenness of a horizontal streak and a vertical streak of an organic EL display device to improve display quality. A silicon oxide film is deposited on a glass...
7521305 Method for fabricating semiconductor device  
A method for fabricating a semiconductor device includes the steps of: providing a semiconductor device formed with a plurality of transistors; forming a first stress layer with a plurality of...
7517760 Semiconductor device manufacturing method including three gate insulating films  
After protective insulating films are formed on first to third active regions, the protective insulating films formed on the first and third active regions are removed. Subsequently, an insulating...
7514332 Semiconductor device and method for manufacturing the same  
A method for manufacturing a semiconductor device includes the steps of (a) forming a first region by selectively ion-implanting a second conductive type impurity into a first conductive type...
7504327 Method of manufacturing thin film semiconductor device  
In the invention, a low concentration impurity region is formed between a channel formation region and a source region or a drain region in a semiconductor layer and covered with a gate electrode...
7501324 Advanced CMOS using super steep retrograde wells  
The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer ( 110 ) beneath the gate dielectric (...
7491605 Zero cost non-volatile memory cell with write and erase features  
A method for making a semiconductor structure of a memory device includes forming a capacitor having a gate dielectric between a gate conductor and a dopant region of a first conductivity type...
7488657 Method and system for forming straight word lines in a flash memory array  
Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same....
7488653 Semiconductor device and method for implantation of doping agents in a channel  
A semiconductor device includes a substrate of a first type of conductivity provided with at least one gate on one of its faces, and at least two doped regions of a second type of conductivity for...
7482220 Semiconductor device having deep trench charge compensation regions and method  
In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the...
7482198 Method for producing through-contacts and a semiconductor component with through-contacts  
A method is described for producing through-contacts through a panel-shaped composite body including semiconductor chips and a plastic mass filled with conductive particles. The panel-shaped...
7470593 Method for manufacturing a cell transistor of a semiconductor memory device  
Disclosed is a method for manufacturing a cell transistor of a semiconductor memory device. The method comprises the steps of: forming device isolation films and a well on a semiconductor...
7465633 Methods of forming field effect transistors and capacitor-free dynamic random access memory cells  
Methods of forming capacitor-free DRAM cells include forming a field effect transistor by forming a first semiconductor wafer having a channel region protrusion extending therefrom and surrounding...
7462543 Flash memory cell transistor with threshold adjust implant and source-drain implant formed using a single mask  
A method for forming an NMOS transistor for use in a flash memory cell on a P-type semiconductor structure includes forming a photoresist layer over the semiconductor structure and patterning the...
7446002 Method for making a semiconductor device comprising a superlattice dielectric interface layer  
A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers adjacent a substrate. Each group of layers of the superlattice may...
7442971 Self-biasing transistor structure and an SRAM cell having less than six transistors  
By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor...
7439165 Method of fabricating tensile strained layers and compressive strain layers for a CMOS device  
A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation...
7439140 Formation of standard voltage threshold and low voltage threshold MOSFET devices  
Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked,...
7432164 Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same  
A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity...
7432160 Semiconductor devices including transistors having three dimensional channels and methods of fabricating the same  
Semiconductor devices including a gate electrode crossing over a semiconductor fin on a semiconductor substrate are provided. A gate insulating layer is provided between the gate electrode and the...
7432136 Transistors with controllable threshold voltages, and various methods of making and operating same  
In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, the active layer being doped with a...
7422948 Threshold voltage adjustment for long channel transistors  
A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with...
7405129 Device comprising doped nano-component and method of forming the device  
A device comprising a doped semiconductor nano-component and a method of forming the device are disclosed. The nano-component is one of a nanotube, nanowire or a nanocrystal film, which may be...
7402495 Method for manufacturing a semiconductor device  
A method of manufacturing a semiconductor device includes forming a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type in a...
7393767 Method for implanting a cell channel ion of semiconductor device  
A method for implanting a cell channel ion of semiconductor device is disclosed. In accordance with the method, the bit line contact region and the edge portion of the channel region adjacent to...
7387908 CMOS imager with enhanced transfer of charge and low voltage operation and method of formation  
A dopant gradient region of a first conductivity type and a corresponding channel impurity gradient below a transfer gate and adjacent a charge collection region of a CMOS imager photodiode are...
7381621 Methods of fabricating high voltage MOSFET having doped buried layer  
A MOSFET includes an insulated gate electrode on a surface of a semiconductor substrate having an impurity region of first conductivity type therein that extends to the surface. Source and drain...
7368356 Transistor with doped gate dielectric  
A transistor and method of manufacture thereof. A semiconductor workpiece is doped before depositing a gate dielectric material. Using a separate anneal process or during subsequent anneal...
7364974 Double gate FET and fabrication process  
A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the...
7354833 Method for improving threshold voltage stability of a MOS device  
This invention provides a method for improving threshold voltage stability of at least one metal-oxide-semiconductor (MOS) device. In one embodiment of the invention, at least one well is formed on...
7351637 Semiconductor transistors having reduced channel widths and methods of fabricating same  
A method of forming a channel in a semiconductor device including forming an opening in a masking layer to expose a portion of an underlying semiconductor layer through the opening is provided. The...
7344966 Manufacturing method for a power device having an auto-aligned double thickness gate layer and corresponding device  
A manufacturing method for a power device integrated on a semiconductor substrate with double thickness of a gate dielectric layer is described, which comprises the following steps: forming first...
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