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Match Document Document Title
8183096 Static RAM cell design and multi-contact regime for connecting double channel transistors  
A static RAM cell may be formed on the basis of two double channel transistors and a select transistor, wherein a body contact may be positioned laterally between the two double channel transistors...
8178862 Junctionless metal-oxide-semiconductor transistor  
A junctionless metal-oxide-semiconductor transistor is described. In one aspect, a transistor device comprises a semiconductor material. The semiconductor material comprises first, second, and...
8148772 Recessed channel array transistor (RCAT) structures  
Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled...
8143130 Method of manufacturing depletion MOS device  
The present invention discloses a method of manufacturing a depletion metal oxide semiconductor (MOS) device. The method includes: providing a substrate; forming a first conductive type well and an...
8133790 Semiconductor device and method for fabricating the same  
A semiconductor device and a method of manufacturing a semiconductor device. A method may include forming a first well by injecting first conduction type impurity ions on and/or over a...
8129246 Advanced CMOS using super steep retrograde wells  
The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50)...
8120105 Lateral DMOS field effect transistor with reduced threshold voltage and self-aligned drift region  
A method of forming a lateral DMOS transistor includes performing a low energy implantation using a first dopant type and being applied to the entire device area. The dopants of the low energy...
8089124 Lateral DMOS device and method for fabricating the same  
An LDMOS device and a method for fabricating the same that may include a first conductivity-type semiconductor substrate having an active area and a field area; a second conductivity-type deep well...
8071434 Method of fabricating a thin film transistor using boron-doped oxide semiconductor thin film  
Provided is a method of fabricating a thin film transistor including source and drain electrodes, a novel channel layer, a gate insulating layer, and a gate electrode, which are formed on a...
8071451 Method of doping semiconductors  
A method of doping a semiconductor body is provided herein. In one embodiment, a semiconductor body is exposed to an activated hydrogen gas for a predetermined time period and temperature. The...
8071444 Nonvolatile semiconductor memory and method of manufacturing the same  
A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer...
8067288 Configuration and method of manufacturing the one-time programmable (OTP) memory cells  
This invention discloses a method for manufacturing a one-time programmable (OTP) memory includes a first and second MOS transistors connected in parallel and controlled by a common gate formed...
8053319 Method of forming a high voltage device  
A method of forming a device is presented. A substrate prepared with an active device region is provided. The active device region includes gate stack layers of a gate stack that includes at least...
8053321 Formation of standard voltage threshold and low voltage threshold MOSFET devices  
Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked,...
8053320 Semiconductor device and manufacturing method thereof  
An aspect of the present invention provides a semiconductor device that includes a first conductivity type semiconductor body, a source region in contact with the semiconductor body, whose bandgap...
8048748 Reducing contamination in a process flow of forming a channel semiconductor alloy in a semiconductor device  
In sophisticated approaches for forming high-k metal gate electrode structures in an early manufacturing stage, a threshold adjusting semiconductor alloy may be deposited on the basis of a...
8048747 Method of manufacturing embedded metal-oxide-nitride-oxide-silicon memory device  
The present disclosure fabricates an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory device. The memory device is stacked with memory layers having a low aspect ratio. The memory device...
8035191 Contact efuse structure  
A contact efuse structure includes a silicon layer and a contact contacting the silicon layer with one end. When a voltage is applied to the contact, a void is formed at the end of the contact, and...
8034695 Semiconductor device and method of manufacturing the same  
A method of manufacturing a semiconductor device comprising the steps of: forming a first silicon oxide film which covers a first region on the top surface of a silicon substrate, but which does...
8030166 Lateral pocket implant charge trapping devices  
A charge trapping memory cell is described, having pocket implants along the sides of the channel and having the same conductivity type as the channel, and which implants have a concentration of...
8013381 Semiconductor device  
A semiconductor device has a semiconductor substrate of a first conductivity type; first to third high-voltage insulated-gate field effect transistors formed on a principal surface of the...
8012836 Semiconductor devices and methods for fabricating the same  
Semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device comprises a substrate with a plurality of isolation structures formed...
8008158 Dopant implantation method using multi-step implants  
A method of forming a dopant implant region in a MOS transistor device having a dopant profile having a target dopant concentration includes implanting a first concentration of dopants into a...
7998849 Semiconductor device used as high-speed switching device and power device  
A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface...
7994012 Semiconductor device and a method of manufacturing the same  
To improve characteristics of a semiconductor device having a nonvolatile memory. There is provided a semiconductor device having a nonvolatile memory cell that performs memory operations by...
7981747 Semiconductor device and a method of manufacturing the same  
A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are...
7981749 MOS structures that exhibit lower contact resistance and methods for fabricating the same  
MOS structures that exhibit lower contact resistance and methods for fabricating such MOS structures are provided. In one method, a semiconductor substrate is provided and a gate stack is...
7982274 Device comprising doped nano-component  
A device comprising a doped semiconductor nano-component and a method of forming the device are disclosed. The nano-component is one of a nanotube, nanowire or a nanocrystal film, which may be...
7977197 Method for fabricating a transistor with reliable source doping  
A transistor and a method for the fabrication of transistors with different gate oxide thicknesses is proposed, in which for the doping of the source, the typical LDD implantation, which is formed...
7968412 Manufacturing process of a vertical-conduction MISFET device with gate dielectric structure having differentiated thickness and vertical-conduction MISFET device thus manufacture  
According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of doping....
7968411 Threshold voltage adjustment for long-channel transistors  
A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with...
7964921 MOSFET and production method of semiconductor device  
To provide a MOSFET which is increased in substrate bias effect γ without increasing parasitic capacitance and junction leak current, the MOSFET includes: a gate electrode (104) formed on a ...
7960798 Structure and method to form multilayer embedded stressors  
A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is...
7947607 Apparatus and associated method for making a virtual ground array structure that uses inversion bit lines  
A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and...
7943468 Penetrating implant for forming a semiconductor device  
A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either...
7943448 Semiconductor device and method of manufacturing the same  
Embodiments relate to a semiconductor device and a method for manufacturing the same. According to embodiments, a semiconductor device may include an LDD which may include a space having a first...
7939898 Diffusion variability control and transistor device sizing using threshold voltage implant  
A transistor is defined to include a substrate portion and a diffusion region defined in the substrate portion so as to provide an operable transistor threshold voltage. An implant region is...
7932166 Field effect transistor having a stressed contact etch stop layer with reduced conformality  
By forming a highly non-conformal stressed overlayer, such as a contact etch stop layer, the efficiency of the stress transfer into the respective channel region of a field effect transistor may be...
7932136 Source/drain junction for high performance MOSFET formed by selective EPI process  
In a field effect transistor (FET), halo features may be formed by etching into the surface of a silicon layer followed by a step of growing a first epitaxial silicon (epi-Si) layer on the etched...
7927987 Method of reducing channeling of ion implants using a sacrificial scattering layer  
Methods and devices for preventing channeling of dopants during ion implantation are provided. The method includes providing a semiconductor substrate and depositing a sacrificial scattering layer...
7913195 Method for creating mask layout data, apparatus for creating mask layout data, and method for manufacturing semiconductor device  
According to mask layout data created for a particular factory facility, transistors constituting a semiconductor device are classified into multiple groups depending on the gate length....
7883976 Structure and method for manufacturing device with planar halo profile  
A semiconductor device and method for manufacturing the device with a planar halo profile is provided. The semiconductor device can be a MOSFET. The method of forming the structure includes forming...
7883977 Advanced CMOS using super steep retrograde wells  
The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50)...
7879678 Methods of enhancing performance of field-effect transistors and field-effect transistors made thereby  
Methods of enhancing the performance of a field-effect transistor (FET) by providing a percolating network of metallic islands to the inversion layer of the FET so as to effectively reduce the...
7880202 Modulated-Vt transistor  
A semiconductor field effect transistor can be used with RF signals in an amplifier circuit. The transistor includes a source region and a drain region with a channel region interposed in between...
7867839 Method to reduce threshold voltage (Vt) in silicon germanium (SiGe), high-k dielectric-metal gate, p-type metal oxide semiconductor field effect transistors  
Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a...
7867861 Semiconductor device employing precipitates for increased channel stress  
A method for fabricating a semiconductor device including implanting a selected material at a desired target depth below a surface of a silicon substrate, performing an annealing process to create...
7863171 SOI transistor having a reduced body potential and a method of forming the same  
By introducing a atomic species, such as carbon, fluorine and the like, into the drain and source regions, as well as in the body region, the junction leakage of SOI transistors may be...
7863140 Methods of making a molecular detection chip having a metal oxide silicon field effect transistor on sidewalls of a micro-fluid channel  
A molecular detection chip including a metal oxide silicon-field effect transistor (MOSFET) on sidewalls of a micro-fluid channel and a molecular detection device including the molecular detection...
7863170 Semiconductor body comprising a transistor structure and method for producing a transistor structure  
A semiconductor body includes a substrate, a buried zone having a first conductivity type that is formed in the substrate, a first zone having the first conductivity type that is above the buried...
Matches 1 - 50 out of 551 1 2 3 4 5 6 7 8 9 10 11 12 >