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Match Document Document Title
7612619 Phase detector device and method thereof  
A device and method for phase detection are disclosed. The device includes a phase differential module that provides a phase difference signal based on the phase difference between a data signal...
7608513 Dual gate LDMOS device fabrication methods  
An N-channel device ( 40, 60 ) is described having a lightly doped substrate ( 42, 42 ′) in which adjacent or spaced-apart P ( 46, 46 ′) and N ( 44 ) wells are provided. A lateral isolation...
7605040 Method of forming high breakdown voltage low on-resistance lateral DMOS transistor  
A method of forming a metal oxide semiconductor (MOS) transistor includes the following steps. A substrate of a first conductivity is provided. A first buried layer of a second conductivity type is...
7601600 Power semiconductor device and method for manufacturing the same  
Disclosed are a power semiconductor device and a method for manufacturing the same. The power semiconductor device has a PIP capacitor and an LDMOS transistor, the LDMOS transistor having second...
7585735 Asymmetric spacers and asymmetric source/drain extension layers  
A method of forming a semiconductor device is provided in which a substrate ( 102 ) is provided which has a gate dielectric layer ( 106 ) disposed thereon, and a gate electrode ( 116 ) having first...
7582533 LDMOS device and method for manufacturing the same  
Provided is a LDMOS device and method for manufacturing. The LDMOS device includes a second conductive type buried layer formed in a first conductive type substrate. A first conductive type first...
7579246 Semiconductor device manufacturing method including oblique ion implantation process and reticle pattern forming method  
An active region and an opposite conductivity active region are formed in a semiconductor substrate. The opposite conductivity active region is covered with a resist pattern. Impurities are...
7579245 Dual-gate metal-oxide-semiconductor device  
An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the...
7575977 Self-aligned LDMOS fabrication method integrated deep-sub-micron VLSI process, using a self-aligned lithography etches and implant process  
An integrated circuit includes both LDMOS devices and one or more low-power CMOS devices that are concurrently formed on a substrate using a deep sub-micron VLSI fabrication process. The LDMOS...
7569883 Switching-controlled power MOS electronic device  
Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors and a gate structure comprising a plurality of conductive strips realized with a first conductive...
7560348 Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in  
A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain...
7560324 Drain extended MOS transistors and methods for making the same  
Drain extended MOS transistors ( 52 ) and fabrication methods ( 100 ) therefor are presented, in which a voltage drop region ( 80 ) is provided in a well ( 82 ) of a second conductivity type...
7557397 Pixel with asymmetric transfer gate channel doping  
A pixel including a substrate of a first conductivity type and having a surface, a photodetector of a second conductivity type that is opposite the first conductivity type, a floating diffusion...
7550804 Semiconductor device and method for forming the same  
A semiconductor device may include a semiconductor substrate having a first dopant type. A first semiconductor region within the semiconductor substrate may have a plurality of first and second...
7550373 Method of forming a salicide layer for a semiconductor device  
Methods of fabricating semiconductor devices are disclosed. An illustrated example method protects spacers and active areas by performing impurity ion implantation on an oxide layer prior to...
7544573 Semiconductor device including MOS field effect transistor having offset spacers or gate sidewall films on either side of gate electrode and method of manufacturing the same  
First and second impurity doped regions are formed in a semiconductor substrate. A first gate electrode is formed on the first impurity doped region with a first gate insulation film interposed...
7541245 Semiconductor device with silicon-film fins and method of manufacturing the same  
A semiconductor device includes a semiconductor substrate, an insulating film projected on a surface of the semiconductor substrate, a semiconductor film provided on a side surface of the...
7541216 Method of aligning deposited nanotubes onto an etched feature using a spacer  
A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature....
7534677 Method of fabricating a dual gate oxide  
A method of fabricating a dual gate oxide of a semiconductor device includes forming a first gate insulation layer over an entire surface of a substrate, removing a portion of the first gate...
7517745 Semiconductor device having MOSFET with offset-spacer, and manufacturing method thereof  
A semiconductor device includes a gate insulating film which is formed on the major surface of a semiconductor substrate, a gate electrode which is formed on the gate insulating film, a first...
7514763 Semiconductor device and manufacturing method for the same  
A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms...
7514330 Semiconductor device having an under stepped gate for preventing gate failure and method of manufacturing the same  
A semiconductor device and a method of manufacturing the same capable of preventing a not open fail of a landing plug contact caused by the leaning of a gate. The method includes the steps of...
7514329 Robust DEMOS transistors and method for making the same  
Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a...
7514325 Fin-FET having GAA structure and methods of fabricating the same  
Example embodiments of the present invention relate to a semiconductor device and methods of fabricating the same. Other example embodiments of the present invention relate to a fin-field effect...
7510941 Semiconductor device and manufacturing method of the same  
The invention improves the performance of a semiconductor device. A metal silicide film is formed by a silicide process on a gate electrode and an n + -type source region of an LDMOSFET, and no...
7507624 Semiconductor memory device and method of manufacturing the same  
A method of manufacturing a semiconductor memory device is provided. The method includes: providing a semiconductor substrate, forming a cell transistor on the semiconductor substrate, and forming...
7498226 Method for fabricating semiconductor device with step gated asymmetric recess  
A method for fabricating a semiconductor device with a step gated asymmetric recess is provided. The method includes: forming an organic bottom anti-reflective coating (BARC) layer over a...
7494882 Manufacturing a semiconductive device using a controlled atomic layer removal process  
A method for manufacturing a semiconductive device comprising forming a mask for a semiconductive device structure over a layer of a semiconductor substrate and partially etching the layer to form...
7491595 Creating high voltage FETs with low voltage process  
An integrated circuit (IC) includes a high voltage first-conductivity type field effect transistor (HV-first-conductivity FET) and a high voltage second-type field effect transistor...
7476591 Lateral power MOSFET with high breakdown voltage and low on-resistance  
A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of the top region of the substrate in...
7465636 Methods for forming semiconductor wires and resulting devices  
Methods for forming a wire from silicon or other semiconductor material are disclosed. Also disclosed are various devices including such a semiconductor wire. According to one embodiment, a wire is...
7446387 High voltage transistor and methods of manufacturing the same  
In a HV transistor having a high breakdown voltage and a method of manufacturing the same, a first insulation pattern is formed on a semiconductor substrate by oxidizing a portion of the substrate,...
7446004 Method for reducing overlap capacitance in field effect transistors  
A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor,...
7446003 Manufacturing process for lateral power MOS transistors  
A process manufactures power MOS lateral transistors together with CMOS devices on a semiconductor substrate. The process forms a lateral MOS transistor having a gate electrode on the semiconductor...
7442613 Methods of forming an asymmetric field effect transistor  
A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant...
7432165 Semiconductor memory device, semiconductor device, and method for production thereof  
Disclosed are a semiconductor memory device, a semiconductor device, and a method for production thereof. The semiconductor memory device and semiconductor device do not need for a distance for...
7429512 Method for fabricating flash memory device  
A method of fabricating a flash memory device. A DDD ion is implanted into a high voltage PMOS transistor and into source and drain junctions of a cell transistor in order to facilitate a pinch-off...
7423319 LDPMOS structure with enhanced breakdown voltage  
A semiconductor structure includes a first well region of a first conductivity type overlying a substrate, a second well region of a second conductivity type opposite the first conductivity type...
7423318 Recessed gate structure with stepped profile  
Disclosed herein are a recess-gate structure in which junctions have a thickness significantly smaller than the thickness of a device isolation layer to thereby prevent shorting of the junctions...
7422949 High voltage transistor and method of manufacturing the same  
The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate;...
7411251 Self protecting NLDMOS, DMOS and extended voltage NMOS devices  
In an NLDMOS, DMOS or NMOS active device the ability to withstand snapback under stress conditions is provided by moving the hot spot away from the drain contact region. This is achieved by moving...
7405128 Dotted channel MOSFET and method  
A improved MOSFET ( 50, 51, 75, 215 ) has a source ( 60 ) and drain ( 62 ) in a semiconductor body ( 56 ), surmounted by an insulated control gate ( 66 ) located over the body ( 56 ) between the...
7396727 Transistor of semiconductor device and method for fabricating the same  
A transistor which may effectively control the short channel effect with a vertical transistor structure. This structure may prevent the degradation of a transistor's performance caused by the hot...
7385261 Extended drain metal oxide semiconductor transistor and manufacturing method thereof  
A MOS transistor having an extended drain structure and including a semiconductor substrate formed in a well of a first conductivity type. A gate insulating layer is formed on the substrate, a gate...
7384845 Methods of fabricating flash memory devices including word lines with parallel sidewalls  
Methods of fabricating integrated circuit devices are provided. The method includes forming a buried diffusion layer in a source active region. A word line pattern is formed crossing over parallel...
7381609 Method and structure for controlling stress in a transistor channel  
A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves forming a shallow-trench-isolation oxide (STI) isolating the...
7378321 Method for patterning a semiconductor component  
In a method for patterning a semiconductor component a first cover layer is applied to a first region and a second region of a semiconductor component being arranged in a semiconductor substrate....
7378320 Method of forming asymmetric MOS transistor with a channel stopping region and a trench-type gate  
A MOS (metal oxide semiconductor) transistor with a trench-type gate is fabricated with a channel stopping region for forming an asymmetric channel region for reducing short channel effects. For...
7374998 Selective incorporation of charge for transistor channels  
A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming...
7371623 Semiconductor device with semiconductor circuit comprising semiconductor units, and method for fabricating it  
The invention is to provide a high-productivity method for fabricating a TFT device having different LDD structures on one and the same substrate, and the TFT device. Specifically, the invention...
Matches 1 - 50 out of 552 1 2 3 4 5 6 7 8 9 10 11 12 >