Matches 351 - 400 out of 554 < 1 2 3 4 5 6 7 8 9 10 11 12 >
Match Document Document Title
5963808 Method of forming an asymmetric bird's beak cell for a flash EEPROM  
A memory cell having an asymmetric source and drain connection to buried bit-lines providing a Fowler-Nordheim tunneling region and a non-tunneling region defined by a bird's beak encroachment on...
5963809 Asymmetrical MOSFET with gate pattern after source/drain formation  
A process for fabricating a transistor in which a first impurity distribution is introduced into a semiconductor substrate prior to the formation of a conductive gate structure on the semiconductor...
5960291 Asymmetric channel transistor and method for making same  
A method for forming an asymmetrical channel transistor is disclosed. The method, in one embodiment, comprises the steps of: forming a gate stack on the surface of the substrate; forming a mask...
5956588 High withstand voltage transistor and method for manufacturing the same  
A high withstand voltage transistor and a method for manufacturing the same are disclosed. The transistor includes a semiconductor substrate, a field oxide film, a channel region formed of first...
5940709 Method and system for source only reoxidation after junction implant for flash memory devices  
A system and method for providing a memory in a semiconductor is disclosed. In one aspect, the method and system include providing a source implant in the semiconductor, providing a first anneal of...
5936277 MOS transistor with impurity-implanted region  
A MOS transistor includes a semiconductor substrate of a first conductivity type having a major surface, a source and drain of a second conductivity type formed on the major surface to define a...
5937298 Method for manufacturing electrostatic discharge protection device  
A method for forming electrostatic discharge protection devices that includes the steps of forming a transistor, which comprises a gate, a source region, a drain region, on a semiconductor...
5930631 Method of making double-poly MONOS flash EEPROM cell  
The present invention discloses a double poly metal oxide/nitride/oxide semiconductor electrically erasable programmable read only memory (EEPROM) for use in semiconductor memories. The EEPROM...
5925914 Asymmetric S/D structure to improve transistor performance by reducing Miller capacitance  
A method of making a transistor is also disclosed, including the steps of forming a gate oxide layer (106) over a semiconductor substrate (100) and forming a gate structure (108) over a portion of...
5923982 Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps  
A method of making the IGFET includes providing a semiconductor substrate, providing a gate over the semiconductor substrate, implanting lightly doped source and drain regions into the substrate,...
5920776 Method of making asymmetric nonvolatile memory cell  
A nonvolatile memory having a cell comprising an N + type source region and drain region embedded in a P - type substrate and surrounded by respective P-pockets. The drain and source P-pockets...
5918125 Process for manufacturing a dual floating gate oxide flash memory cell  
An improved floating gate memory cell, having a dual thickness floating gate oxide, minimizes the band-to-band tunneling current and hot hole injection current suffered by the device, maximizes the...
5918128 Reduced channel length for a high performance CMOS transistor  
An integrated circuit fabrication process is provided in which a transistor having an ultra short channel length is formed by multiple etchings of a gate conductor layer. After formation of the...
5915176 Method of making floating gate based memory device  
Semiconductor memory device and method is provided for a stacked gate type flash semiconductor memory device. The semiconductor memory device improves programming and erasing operation efficiency....
5915178 Method for improving the endurance of split gate flash EEPROM devices via the addition of a shallow source side implanted region  
A process for fabricating a flash EEPROM device, incorporating a shallow, heavily doped, source side region, used to improve the endurance of the flash EEPROM device, has been developed. The...
5909622 Asymmetrical p-channel transistor formed by nitrided oxide and large tilt angle LDD implant  
Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a...
5904529 Method of making an asymmetrical IGFET and providing a field dielectric between active regions of a semiconductor substrate  
A method of making an asymmetrical IGFET and isolating active regions is disclosed. The method includes providing a semiconductor substrate with an active region and a field region, wherein the...
5899718 Method for fabricating flash memory cells  
A method for fabricating flash memory cells having a DDD structure that prevents leakage current during data erasure, that does not require a high temperature drive-in process, and that easily...
5897354 Method of forming a non-volatile memory device with ramped tunnel dielectric layer  
The invention relates to a method of forming a non-volatile memory device with a ramped tunnel dielectric layer, in which a floating gate material layer is being oxidized such that a tunnel...
5893739 Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer  
Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a...
5891774 Method of fabricating EEPROM using oblique implantation  
A semiconductor memory device is provided which comprises: a plurality of memory cell transistors each having a tunnel oxide film formed on a semiconductor substrate of a first conductivity type, a...
5891757 Method for forming a field-effect transistor having difference in capacitance between source and drain with respect to shield layer  
A field-effect transistor has a source region, a drain region, a gate electrode, and a low resistivity layer. The source and drain regions are of a first conductivity type and formed as surface...
5882973 Method for forming an integrated circuit having transistors of dissimilarly graded junction profiles  
An integrated circuit is provided having a plurality of transistors either NMOS transistors, or PMOS transistors, or both NMOS and PMOS transistors. The transistors are formed having dissimilarly...
5882974 High-performance PMOS transistor using a barrier implant in the source-side of the transistor channel  
The present invention advantageously provides a method for forming a transistor having decreased source-side parasitic resistance and an improved shallow junction, thereby providing for enhanced...
5879995 High-voltage transistor and manufacturing method therefor  
A fourth impurity region having a smaller junction depth than that of the second impurity region, and having a third impurity concentration which is lower than that of the second impurity region is...
5879999 Method of manufacturing an insulated gate semiconductor device having a spacer extension  
An insulated gate semiconductor device (10) having a gate structure (45) that includes a conductive spacer (32) and an extension region (46) extending from the conductive spacer (32). To form the...
5877050 Method of making N-channel and P-channel devices using two tube anneals and two rapid thermal anneals  
A method of making N-channel and P-channel IGFETs is disclosed. The method includes, in sequence, the steps of partially doping a first source and a first drain in a first active region of a...
5874340 Method for fabrication of a non-symmetrical transistor with sequentially formed gate electrode sidewalls  
The method for fabrication of a non-symmetrical IGFET of the present invention includes providing a semiconductor substrate having an insulating film and a gate material. A first portion of the...
5866460 Method of forming a multiple inplant lightly doped drain (MILDD) field effect transistor  
A multiple implant lightly doped drain ("MILDD") field effect transistor is disclosed. The transistor includes a channel, a gate, a dielectric structure that separates the gate from the channel, a...
5849616 Method of manufacturing a semiconductor device  
A semiconductor device comprises a semiconductor substrate (11) having first and second field effect transistors. Each transistor includes a gate electrode (17, 18) formed on the semiconductor...
5849622 Method of forming a source implant at a contact masking step of a process flow  
In the fabrication of an integrated circuit having both N MOSFETs and P MOSFETs in which the respective N-type species and P-type species have substantially different diffusivities, the source...
5837572 CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein  
An integrated circuit is provided having both NMOS transistors and PMOS transistors. The NMOS transistor junction regions are preferably formed before the PMOS transistor junction regions with...
5830788 Method for forming complementary MOS device having asymmetric region in channel region  
A complementary semiconductor device which includes: a semiconductor substrate having a principal surface, with a first region doped with an impurity of a first conductivity type and a second...
5828104 MOS structure device having asymmetric LDD structure and fabrication method thereof  
An MOS semiconductor device containing an MOSFET with an asymmetric LDD structure, which has in a semiconductor substrate a first heavily doped region, a lightly doped region formed adjacent to the...
5811338 Method of making an asymmetric transistor  
In one aspect, a method for forming a transistor device on a semiconductor substrate, comprising: a) forming a transistor gate on the. substrate; b) forming a first polarity source active region...
5811341 Differential amplifier having unilateral field effect transistors and process of fabricating  
A differential amplifier (10) includes three unilateral field effect transistors (12, 14, 16) formed in a common well (40) of a semiconductor material. Each of the three unilateral field effect...
5811324 Method for manufacturing thin film transistor  
A thin film transistor includes a first active layer formed on a substrate; a gate electrode formed on a center portion of the first active layer and having a lower side connected to the center...
5789282 Method for fabricating thin film transistor  
A method for fabricating a thin film transistor, comprising the steps of: forming a gate electrode; forming a doped polysilicon film for source/drain at the side wall of the gate electrode, to...
5773345 Optical link amplifier and a wavelength multiplex laser oscillator  
The present invention provides an optical link amplifier which reduces the attenuation of the optical signal passing through optical an link amplifier so as to have a fail-safe function to ensure...
5770880 P-collector H.V. PMOS switch VT adjusted source/drain  
A PMOS device has an n-type body 12 and a triple source drain diffusion. A first drain region 14 is heavily p-doped to provide ohmic contact to the drain. A lightly doped drain region 16 extends to...
5763308 Method for fabricating flash memory cells using a composite insulating film  
A flash memory cell, comprising: a composite insulating film formed on a substrate at a predetermined size which charges are trapped or detrapped; a drain formed at one side of the composite...
5750416 Method of forming a lateral field effect transistor having reduced drain-to-source on-resistance  
A power field effect transistor has a laterally extending channel region which is not formed by double diffusion. The channel region may be formed in epitaxial silicon which is not doped after...
5741736 Process for forming a transistor with a nonuniformly doped channel  
A semiconductor device (83)including a transistor (85) with a nonuniformly doped channel region can be formed with a relatively simple process without having to use high dose implants or additional...
5741718 Method for manufacturing a semiconductor device  
In forming a thin film transistor (TFT) having an offset structure or a lightly doped drain (LDD) structure, a blocking material having a lower etching rate than that of a material constructing a...
5739061 Method of manufacturing a semiconductor device using gate side wall as mask for self-alignment  
A method of manufacturing a BiCMOS apparatus including a DMOS is disclosed which reduces manufacturing steps, shortens manufacturing time and reduces manufacturing cost. A channel ion implanted...
5736418 Method for fabricating a field effect transistor using microtrenches to control hot electron effects  
According to the present invention, there is provided a method for fabricating a field effect transistor having reduced hot electron effects. In one embodiment, the method comprises the steps of...
5716866 Method of forming a semiconductor device  
A method for forming a unilateral, graded-channel field effect transistor and a transistor stock 200 that includes providing a substrate (10) with an overlying gate electrode (14, 16). A spacer...
5705439 Method to make an asymmetrical LDD structure for deep sub-micron MOSFETS  
A method for forming an asymmetrical LDD structure is described. A polysilicon gate electrode is formed overlying a layer of gate silicon oxide on the surface of a semiconductor substrate. The...
5698457 Method for manufacturing high voltage semiconductor device  
A high voltage semiconductor device includes a low voltage CMOSFET and a p-channel high voltage MOSFET having a drain formed in a p-well and a source in an n-well. The p-well has a bottom flush...
5696010 Method of forming a semiconductor device including a trench  
A high voltage power transistor cell is developed that provides improved RDSon performance without sacrificing breakdown performance through utilization of trench based transistor technology. A...
Matches 351 - 400 out of 554 < 1 2 3 4 5 6 7 8 9 10 11 12 >