Matches 301 - 350 out of 554 < 1 2 3 4 5 6 7 8 9 10 11 12 >
Match Document Document Title
6107160 MOSFET having buried shield plate for reduced gate/drain capacitance  
Gate to drain capacitance in a lateral DMOS and vertical DMOS field effect transistor is minimized by providing a conductive shield plate under the gate and between the gate and the drain of the...
6100141 Method for forming electrostatic discharge (ESD) protection circuit  
A method for forming a dual-thickness gate oxide layer starts with forming and patterning a pad oxide layer and a silicon nitride layer on a substrate. The substrate contains pre-determined regions...
6096610 Transistor suitable for high voltage circuit  
A method and an apparatus for forming a transistor suitable for a high voltage circuit. In one embodiment, the transistor is formed without adding any steps to an existing state-of-the-art CMOS...
6096605 Fabricating method of non-volatile flash memory device  
A method of fabricating a non-volatile flash memory device, wherein a gate structure is formed on a substrate. The method includes at least the following steps. The substrate is implanted with...
6093609 Method for forming semiconductor device with common gate, source and well  
A method has a feature that one side of the spacers surrounding a gate of a MOS transistor is removed and another side of the spacers is exposed. By the method of this invention, the gate, the...
6090670 Highly efficient transistor for fast programming of flash memories  
In a semiconductor fabrication method for forming a transistor structure upon a semiconductor substrate, a nitride layer is also formed over the semiconductor substrate. A gate oxide layer is...
6087232 Fabrication method of lateral double diffused MOS transistors  
According to a method for manufacturing double RESURF (reduced SURface Field) LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistors, on-resistance of double RESURF LDMOS transistors has...
6087221 Method of fabricating two dissimilar devices with diminished processing steps  
A method for fabricating dissimilar devices in an integrated circuit. In one embodiment, the method can be used to fabricate flash memory, including MOS transistors and flash cells. The method can...
6083794 Method to perform selective drain engineering with a non-critical mask  
A method of producing an asymmetrical semiconductor device with ion implantation techniques and semiconductor devices constructed according to this method in which a barrier of ion absorbing...
6078060 Active matrix display devices and methods of manufacturing the active matrix display devices  
The invention provides a peripheral drive circuit integrated active matrix LCD device in which thin-film transistors have different characteristics optimized for individual circuits of the active...
6066534 Method of manufacturing a field effect transistor  
A field effect transistor includes a semiconductor substrate; a gate insulating film on the semiconductor substrate; a first impurity region and a second impurity region formed in a surface of the...
6066531 Method for manufacturing semiconductor memory device  
A method for manufacturing a semiconductor memory device, including the steps of: forming a plurality of stripes comprising a first floating gate material film and a ion implantation protective...
6063674 Method for forming high voltage device  
A method for forming high voltage devices is provided. A P-type semiconductor substrate is provided. An oxide layer is formed on the P-type semiconductor substrate. A first P-well and a second...
6063671 Method of forming a high-voltage device  
A method of forming a high-voltage device is provided. A substrate with a first electrical type is provided. A first doped region with a second electrical type is formed in a portion of the...
6060346 Semiconductor device and method for manufacturing the same  
A semiconductor device and a method for manufacturing the same that forms a self-aligned contact hole between two gate lines. A substrate is provided that has a first gate line formed thereon. An...
6051471 Method for making asymmetrical N-channel and symmetrical P-channel devices  
An asymmetrical N-channel IGFET and a symmetrical P-channel IGFET are disclosed. The N-channel IGFET includes heavily doped and ultra-heavily doped source regions, and lightly doped and heavily...
6051458 Drain and source engineering for ESD-protection transistors  
A semiconductor device is formed on a semiconductor substrate with an N-well and a P-well with source/drain sites in the N-well and in the P-well by the following steps. Form a gate oxide layer and...
6048770 Nonvolatile semiconductor memory device and method of manufacturing the same  
Under an N - -drain region covering an N + -drain region, a P + -impurity region is formed without covering an end of the N - -drain region near a channel region. Thereby, the P + -impurity...
6048776 Semiconductor device and a method of fabricating the same  
A method of fabricating a semiconductor device, comprises the steps of forming a trench in a semiconductor substrate by using a selective etching process; forming an insulating layer at least on...
6040220 Asymmetrical transistor formed from a gate conductor of unequal thickness  
An asymmetrical transistor, and a gate conductor used in forming that transistor, are provided. The gate conductor is formed by removing upper portions of the gate conductor along an elongated axis...
6040249 Method of improving diffusion barrier properties of gate oxides by applying ions or free radicals of nitrogen in low energy  
A method of providing a MOSFET having improved gate oxide diffusion barrier properties, which comprises providing a partially fabricated MOSFET having an exposed gate oxide surface. During MOSFET...
6037226 Method of making contactless nonvolatile semiconductor memory with asymmetrical floating gate  
A contactless, nonvolatile metal oxide semiconductor memory device having a rectangular array of memory cells interconnected by word-lines in the row direction of the array and bit-lines in the...
6027978 Method of making an IGFET with a non-uniform lateral doping profile in the channel region  
A method of making an IGFET with a selectively doped channel region is disclosed. The method includes providing a semiconductor substrate with a device region, forming a gate over the device...
6025229 Method of fabricating split-gate source side injection flash memory array  
A split-gate source side injection flash memory structure that utilizes the polysilicon spacers formed on the sidewalls of the control gate and the floating gate, and the difference in...
6025231 Self aligned DMOS transistor and method of fabrication  
A method for fabricating a self-aligned DMOS transistor is provided. The method includes forming a passivation layer (18, 68) on an oxide layer (16, 66) of a substrate (12, 56). The oxide layer...
6022815 Method of fabricating next-to-minimum-size transistor gate using mask-edge gate definition technique  
A method of fabricating minimum size and next-to-minimum size electrically conductive members using a litho-less process is disclosed. A substrate is provided, and a layer of gate dielectric...
6022780 Semiconductor device having source and drain regions different in depth from each other and process of fabrication thereof  
A side wall spacer and a spacer layer are concurrently formed from an insulating layer in such a manner that the side wall spacer is on one side surface of a gate electrode and the spacer layer...
6020232 Process of fabricating transistors having source and drain regions laterally displaced from the transistors gate  
An integrated circuit comprising a semiconductor substrate, a gate dielectric formed on an upper surface of the semiconductor substrate, a first and a second conductive gate formed on the gate...
6020227 Fabrication of multiple field-effect transistor structure having local threshold-adjust doping  
A structure containing multiple field-effect transistors (60 and 150) is fabricated from a semiconductor body having material (82) of a specified conductivity type. Semiconductor dopant of the...
6020242 Effective silicide blocking  
A metal silicide blocking process for preventing formation of metal silicide on a first device and allowing formation of metal silicide on elements of a second device of an integrated circuit...
6017798 FET with stable threshold voltage and method of manufacturing the same  
A low voltage field effect transistor structure (20) is provided with a threshold voltage that is tolerant of process variations that alter the location of a source implant region (41). A first...
6017797 Method of fabricating a semiconductor device including complementary MOSFET and power MOSFET  
There is provided a method of fabricating a semiconductor device including, a first conductivity type MOSFET, a second conductivity type MOSFET, and a power MOSFET having a high breakdown voltage,...
6011289 Metal oxide stack for flash memory application  
In order to alleviate lifting problems and to reduce the height of the stack, a tungsten layer is formed on a interpoly dielectric layer, such as an ONO layer, which separates the conductive...
6011276 Thin film transistor and fabrication method thereof  
A thin film transistor and a fabrication method thereof which are capable of increasing an ON/OFF current ratio and simplifying a fabrication process by eliminating a masking process. The thin film...
6004849 Method of making an asymmetrical IGFET with a silicide contact on the drain without a silicide contact on the source  
A method of making an asymmetrical IGFET is disclosed. The method includes providing a semiconductor substrate with an active region, wherein the active region includes a source region and a drain...
6004137 Method of making graded channel effect transistor  
A MISFET having a graded semiconductor alloy channel layer of silicon germanium in which the germanium is graded to a single peak percentage level. The single peak percentage level defines the...
6001689 Process for fabricating a flash memory with dual function control lines  
A flash memory formed by a process wherein at least two parallel stacked gate strips are formed on a silicon substrate such that the stacked gate strips are separated by field oxide islands....
6001710 MOSFET device having recessed gate-drain shield and method  
A method of fabricating a MOSFET transistor and resulting structure having a drain-gate feedback capacitance shield formed in a recess between a gate electrode and the drain region. The shield does...
5998265 Method of manufacturing EPROM device  
On a semiconductor substrate, a floating gate electrode composed of a first layer of polysilicon is disposed through a gate dielectric film, and the drain diffusion layer contacts with the floating...
5997638 Localized lattice-mismatch-accomodation dislocation network epitaxy  
The present invention is a layered structures of substantially-crystalline semiconductor materials and processes for making such structures. More particularly, the invention epitaxial grows a...
5994185 Method of fabricating flash memory cell  
A method of fabricating a flash memory. A heavily doped region with the opposite polarity of the drain region is formed between the channel region and the drain region. The heavily doped region is...
5989967 Transistor with ultra short length defined partially by sidewall oxidation of a gate conductor overlying the channel length  
An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length. A mask is formed, from a material resistant to oxidation, upon a conductive gate...
5989339 MBE system and semiconductor device fabricated, using same  
A molecular beam epitaxy system having a plurality of chambers which contain at least a first chamber and a second chamber. The first chamber is used to form II-VI column compound semiconductor...
5985707 Semiconductor memory device with improved current control through an access transistor and method thereof  
A semiconductor memory device and a fabrication method thereof include formation of surplus gates connected to a cell node of a gate edge region, located at a cell node side of a SRAM access...
5985724 Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spacer  
Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a...
5976925 Process of fabricating a semiconductor devise having asymmetrically-doped active region and gate electrode  
A semiconductor device having asymmetrically-doped gate electrode and active region and a process of fabricating such a device is provided. According to one embodiment of the invention, a...
5970349 Semiconductor device having one or more asymmetric background dopant regions and method of manufacture thereof  
Semiconductor devices having one or more asymmetric background dopant regions and methods of fabrication thereof are provided. The asymmetric background dopant regions may be formed using a...
5970348 Read-only memory and corresponding method of manufacturing by MOS technology  
In a method for the manufacture of cells of a read-only memory, each cell comprises a MOS transistor formed by a first diffusion and a second diffusion of impurities of a first type in a...
5970347 High performance mosfet transistor fabrication technique  
A semiconductor fabrication process in which nitrogen is incorporated into the transistor gate without significantly increasing the resistivity of the source/drain region. The incorporation of...
5966617 Multiple local oxidation for surface micromachining  
A multiple LOCOS (local oxidation) process shapes a surface of a substrate to form a series of planar regions which are vertically separated from each other. One exemplary process forms a hard mask...
Matches 301 - 350 out of 554 < 1 2 3 4 5 6 7 8 9 10 11 12 >