Matches 151 - 200 out of 553 < 1 2 3 4 5 6 7 8 9 10 11 12 >
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6773978 Methods for improved metal gate fabrication  
Methods are disclosed for manufacturing semiconductor devices with silicide metal gates, wherein a single-step anneal is used to react a metal such as cobalt or nickel with substantially all of a...
6773997 Method for manufacturing a high voltage MOSFET semiconductor device with enhanced charge controllability  
A high voltage MOSFET device ( 100 ) has an nwell region ( 113 ) with a p-top layer ( 108 ) of opposite conductivity formed to enhance device characteristics. The p-top layer is implanted through a...
6773998 Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning  
A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of...
6767778 Low dose super deep source/drain implant  
A semiconductor device for reducing junction capacitance by an additional low dose super deep source/drain implant and a method for its fabrication are disclosed. In particular, the super deep...
6753217 Method for making self-registering non-lithographic transistors with ultrashort channel lengths  
In a method for making transistors with ultrashort channel length, the deposition of respectively source, drain and gate electrodes initially can be performed with prior art technology limiting the...
6753227 Method of fabricating MOS transistors  
A method of fabricating a MOS transistor is provided. According to the method, a rapid thermal anneal is applied to a semiconductor substrate having active regions doped with well impurity ions and...
6746920 Fabrication method of flash memory device with L-shaped floating gate  
The present invention generally relates to provide a fabrication method of a flash memory with L-shaped floating gate. The present invention utilizes a dielectric spacer on a surface of a...
6746924 Method of forming asymmetric extension mosfet using a drain side spacer  
A method of forming an asymmetric extension MOSFET using a drain side spacer which allows a choice of source and drain sides for each individual MOSFET device and also allows an independent design...
6723662 Methods of forming gate oxide films in integrated circuit devices using wet or dry oxidization processes with reduced chloride  
Methods of forming gate oxide films in integrated circuit devices using wet or dry oxidization processes with a reduced amount of chloride are disclosed. A gate oxide film is formed on a substrate...
6720228 Current source bias circuit with hot carrier injection tracking  
A current mirror bias circuit for an RF amplifier transistor is modified whereby the reference transistor of the current mirror tracks hot carrier degradation in the RF transistor. Gate bias to the...
6713333 Method for fabricating a MOSFET  
The disclosed invention provides a method for fabricating a MOSFET comprising the steps of forming a first insulation layer over a semiconductor substrate; forming a trench which bottoms on the...
6713346 Methods of forming a line of flash memory cells  
The invention comprises FLASH memory and methods of forming flash memory. In one implementation, a line of floating gates is formed over a semiconductor substrate. The semiconductor substrate is...
6706571 Method for forming multiple structures in a semiconductor device  
A method of forming multiple structures in a semiconductor device includes depositing a film over a conductive layer, etching a trench in a portion of the film and forming adjacent the sidewalls of...
6699740 Method for manufacturing a lateral double-diffused MOS transistor having stable characteristics and equal drift length  
A semiconductor device including a P-type semiconductor layer; an N-type first well on the surface of the semiconductor layer; a P-type second well on the surface of the first well; an N-type...
6693323 Super-junction semiconductor device  
A method of manufacture reduces costs and provides an excellent mass-productivity, a super-junction semiconductor device, that facilitates reducing times of heat treatment of the alternating...
6686245 Vertical MOSFET with asymmetric gate structure  
A semiconductor fabrication process and structure in which a semiconductor channel structure ( 140 ) having first and second major surfaces perpendicular to a semiconductor substrate ( 102 ) is...
6682980 Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant  
The present invention is directed to a method of forming a PMOS transistor within a semiconductor substrate, and comprises forming a gate over an n-type portion of the semiconductor substrate,...
6680231 High-voltage device process compatible with low-voltage device process  
A high-voltage device process compatible with a low-voltage device process. A high-voltage device area and a low-voltage device area are defined on an epitaxial layer of a semiconductor substrate....
6660596 Double planar gated SOI MOSFET structure  
A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow...
6660578 High-K dielectric having barrier layer for P-doped devices and method of fabrication  
A semiconductor device, a semiconductor wafer and a method of forming a semiconductor wafer where a barrier layer is used to inhibit P-type ion-penetration into a dielectric layer made from a...
6653193 Resistance variable device  
A resistance variable device and a method for using the same. The device includes a body formed of a voltage or current controlled resistance setable material, and at least two spaced electrodes on...
6638842 Methods of fabricating integrated circuitry  
A method of fabricating integrated circuitry comprises forming a conductive line having opposing sidewalls over a semiconductor substrate. An insulating layer is then deposited. The insulating...
6632716 Semiconductor device and manufacturing method thereof  
A semiconductor device is comprised of: an element isolating film formed on one major surface of a semiconductor substrate; an element forming region formed on the major surface and surrounded by...
6624057 Method for making an access transistor  
Methods are disclosed for the fabrication of novel polysilicon structures having increased surface areas to achieve lower resistances after silicidation. The structures are applicable, for example,...
6620688 Method for fabricating an extended drain metal oxide semiconductor field effect transistor with a source field plate  
An extended drain metal oxide semiconductor field effect transistor (EDMOSFET) with a source field plate is provided. The EDMOSFET includes: a first-conductivity type semiconductor substrate; a...
6620656 Method of forming body-tied silicon on insulator semiconductor device  
An integrated circuit using silicon-on-insulator (SOI) has most of its transistors with their channels (bodies) floating. Some of the transistors, however, must have their channels coupled to a...
6613633 Method for manufacturing a high power semiconductor device having a field plate extendedly disposed on a gate  
A method to fabricate a high voltage transistor of a smart power device is discussed. The method includes forming a well of first conductivity in a substrate of second conductivity; forming a drift...
6610576 Method for forming asymmetric dual gate transistor  
The present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention...
6596594 Method for fabricating field effect transistor (FET) device with asymmetric channel region and asymmetric source and drain regions  
Within a method for fabricating a field effect transistor (FET) device there is provided a series of ion implant methods which provide the field effect transistor (FET) device with both: (1) a...
6597044 Semiconductor device having a charge removal facility for minority carriers  
The invention relates to a high-voltage deep depletion transistor, provided in a semiconductor body ( 1 ) having a substrate ( 2 ) of a first conductivity type, for example the p-type, and a...
6576520 Amorphous carbon layer for improved adhesion of photoresist and method of fabrication  
An improved and novel semiconductor device including an amorphous carbon layer for improved adhesion of photoresist and method of fabrication. The device includes a substrate having a surface, a...
6569731 Method of forming a capacitor dielectric structure  
A method of forming capacitor dielectric structure. The method includes steps of providing a semiconductor substrate having at least a predetermined capacitor structure, using silicon nitride...
6566204 Use of mask shadowing and angled implantation in fabricating asymmetrical field-effect transistors  
To furnish an IGFET ( 120 or 122 ) with an asymmetrically doped channel zone ( 144 or 164 ), a mask ( 212 ) is provided over a semiconductor body and an overlying electrically insulated gate...
6563176 Asymmetrical semiconductor device for ESD protection  
An asymmetrical ESD protection device and a method of production thereof are provided. A source region and a drain region are formed in a substrate. A gate is formed over the substrate between the...
6559019 Breakdown drain extended NMOS  
An MOS device and the method of making the device which includes a semiconductor substrate having a well therein of predetermined conductivity type. A tank having a surface is disposed within the...
6548355 EEPROM memory cell and corresponding manufacturing method  
An EEPROM memory cell integrated in a semiconductor substrate comprises a floating gate MOS transistor having a source region, a drain region, and a gate region projecting from the substrate and is...
6544850 Dynamic random access memory  
A dynamic random access memory (DRAM) formed in a silicon chip that includes a support area in which support circuitry of the memory includes a single electrical contact through two dielectric...
6541320 Method to controllably form notched polysilicon gate structures  
A method and structure for forming a notched gate structure having a gate conductor layer on a gate dielectric layer. The gate conductor layer has a first thickness. The inventive method includes...
6541393 Method for fabricating semiconductor device  
A semiconductor device is fabricated by a method comprising the steps of: selectively introducing a halogen element or argon into a device region 14 of a silicon substrate 10 ; and wet oxidizing...
6537884 Semiconductor device and method of manufacturing the same including an offset-gate structure  
A semiconductor device having an offset-gate structure, which can achieve a release of an electric field concentration and a lowering a transistor resistance at the same time. A semiconductor...
6531355 LDMOS device with self-aligned RESURF region and method of fabrication  
A RESURF LDMOS transistor ( 64 ) includes a RESURF region ( 42 ) that is self-aligned to a LOCOS field oxide region ( 44 ). The self-alignment produces a stable breakdown voltage BVdss by...
6528372 Sidewall spacer definition of gates  
A method of forming features on a semiconductor device uses sidewall spacers, and includes providing a sidewall template having first and second sidewall regions. A spacer layer of a spacer...
6524914 Source side boron implanting and diffusing device architecture for deep sub 0.18 micron flash memory  
One aspect of the present invention relates to a method of making a flash memory cell involving the steps of providing a substrate having a flash memory cell thereon; forming a self-aligned source...
6518138 Method of forming Self-aligned lateral DMOS with spacer drift region  
An LDMOS transistor formed in an N-type substrate. A polysilicon gate is formed atop the N-type substrate. A P-type well is formed in the N-type substrate extending from the source side to under...
6514829 Method of fabricating abrupt source/drain junctions  
A method of fabricating an integrated circuit forming abrupt source/drain junctions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors...
6509237 Flash memory cell fabrication sequence  
An abrupt drain junction and a graded source junction are fabricated using a common diffusion step, wherein the common diffusion step is used to create both the drain junction-and the source...
6506648 Method of fabricating a high power RF field effect transistor with reduced hot electron injection and resulting structure  
Methods of fabricating a high power RF lateral diffused MOS transistor (LDMOS) having increased reliability includes fabricating an N-drift region for the drain prior to fabrication of the gate...
6506649 Method for forming notch gate having self-aligned raised source/drain structure  
An innovative MOSFET having a raised source drain (RSD) is constructed prior to implanting source-drain dopants. The RSD structure thus built has a distinct advantage in that the offset from the...
6506642 Removable spacer technique  
Submicron-dimensioned MOS and/or CMOS transistors are fabricated utilizing a simplified removable sidewall spacer technique, enabling effective tailoring of individual transistors to optimize their...
6500739 Formation of an indium retrograde profile via antimony ion implantation to improve NMOS short channel effect  
A method of forming a pocket implant region, to reduce short channel effects (SCE), for narrow channel length, NMOS devices, has been developed. After forming an indium pocket implant region, in...
Matches 151 - 200 out of 553 < 1 2 3 4 5 6 7 8 9 10 11 12 >