Matches 1 - 50 out of 179 1 2 3 4 >
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7629641 Band engineered nano-crystal non-volatile memory device utilizing enhanced gate injection  
Non-volatile memory devices and arrays are described that utilize reverse mode non-volatile memory cells that have band engineered gate-stacks and nano-crystal charge trapping in EEPROM and block...
7605059 Semiconductor device and method of manufacturing the semiconductor device  
A semiconductor device comprises: a MOS transistor including: a semiconductor substrate; a source region, formed in the semiconductor substrate, that comprises an impurity of a first conductive...
7575950 Semiconductor device and a method of manufacturing the same  
A semiconductor device having improved performance and improvement manufacturing yield is provided. After a semiconductor integrated circuit including a phase change memory and a nonvolatile memory...
7560345 Method of assessing potential for charging damage in integrated circuit designs and structures for preventing charging damage  
A method for preventing charging damage during manufacturing of an integrated circuit design, having silicon over insulator (SOI) transistors. The method prevents damage from charging during...
7554164 Semiconductor device having a gap between a gate electrode and a dummy gate electrode  
A method of deforming a pattern comprising the steps of: forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper...
7553704 Antifuse element and method of manufacture  
An antifuse element ( 102, 152, 252, 302, 352, 402, 602, 652, 702 ) and method of fabricating the antifuse element, including a substrate material ( 101 ) having an active area ( 106 ) formed in an...
7535078 Semiconductor device having a fuse and method of forming thereof  
A fuse ( 43 ) is formed overlying a passivation layer ( 35 ) and under a packaging material ( 55, 70 ). In one embodiment, a fuse ( 43 ) is blown before the packaging material ( 55, 70 ) is formed....
7534671 Method for integrally forming an electrical fuse device and a MOS transistor  
A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps. An isolation structure is formed on...
7531388 Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabricating thereof  
Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element....
7521266 Production and packaging control for repaired integrated circuits  
A method for reducing the scrap rate of fuse structures after laser repairing is provided. The method includes providing a semiconductor wafer comprising integrated circuits, performing a yield...
7517763 Semiconductor device having fuse and capacitor at the same level and method of fabricating the same  
In a semiconductor device and a method of fabricating the same, a fuse and a capacitor are formed at a same level on a semiconductor substrate having a fuse area and a capacitor area. The fuse is...
7517762 Semiconductor device capable of preventing moisture-absorption of fuse area thereof and method for manufacturing the fuse area  
A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of...
7495309 Semiconductor device and manufacturing method thereof  
A redundant fuse is provided with a redundant length, here a winding structure, at one end thereof, here at a vicinity of a second wire side to which a high voltage (Vcc) is impressed. A...
7491585 Electrical fuse and method of making  
A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method...
7470590 Methods of forming semiconductor constructions  
The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the...
7459350 Method for fabricating a protection circuit located under fuse window  
A method for making a semiconductor device having a fuse window above a substrate is disclosed. The semiconductor device has at least one fuse protection circuit located under the fuse window. The...
7442626 Rectangular contact used as a low voltage fuse element  
A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse elements. In one embodiment, the fuse...
7442596 Methods of manufacturing fin type field effect transistors  
A fin type field effect transistor includes a semiconductor substrate, an active fin, a first hard mask layer pattern, a gate insulation layer pattern, a first conductive layer pattern, and...
7413936 Method of forming copper layers  
A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends...
7402887 Semiconductor device having fuse area surrounded by protection means  
A semiconductor device has a semiconductor substrate, first and second insulating layers, a fuse, a diffusion layer and a conductive pattern. The first insulating layer is selectively formed on a...
7402464 Fuse box of semiconductor device and fabrication method thereof  
A fuse box includes a semiconductor substrate having a fuse region, and a lower line in the fuse region that has a first region and a second region. An upper line is placed on the upper part of the...
7387937 Thermal dissipation structures for FinFETs  
A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate...
7381594 CMOS compatible shallow-trench efuse structure and method  
A semiconductor structure including at least one e-fuse embedded within a trench that is located in a semiconductor substrate (bulk or semiconductor-on-insulator) is provided. In accordance with...
7354805 Method of making electrically programmable fuse for silicon-on-insulator (SOI) technology  
A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator...
7352050 Fuse region of a semiconductor region  
In a fuse region of a semiconductor device, and a method of fabricating the same, the fuse region includes an interlayer insulating layer on a semiconductor substrate, a plurality of fuses on the...
7335537 Method of manufacturing semiconductor device including bonding pad and fuse elements  
A method of manufacturing a semiconductor device includes forming a first insulating film supported by a semiconductor substrate, forming an aluminum layer supported by the first insulating film,...
7323389 Method of forming a FINFET structure  
A semiconductor device ( 10 ) such as a FinFET transistor of small dimensions is formed in a process that permits substantially uniform ion implanting ( 32 ) of a source ( 14 ) electrode and a...
7314815 Manufacturing method of one-time programmable read only memory  
An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping...
7306998 Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect  
A method of forming an abrupt junction device with a semiconductor substrate is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A...
7268047 Semiconductor device and method for manufacturing the same  
A gate insulating film on a silicon substrate of includes a SiO 2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon...
7242072 Electrically programmable fuse for silicon-on-insulator (SOI) technology  
A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator...
7118951 Method of isolating the current sense on power devices while maintaining a continuous stripe cell  
An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal...
7092273 Low voltage non-volatile memory transistor  
A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate...
7087974 Semiconductor integrated circuit including anti-fuse and method for manufacturing the same  
An anti-fuse is manufactured by forming an isolation region including an insulating material layer buried in a surface of a device formation region on a surface of a semiconductor substrate, and by...
7075127 Single-poly 2-transistor based fuse element  
An electrically programmable transistor fuse having a double-gate arrangement disposed in a single layer of polysilicon in which a first gate is disposed overlapping a portion of a source region...
7067897 Semiconductor device  
A semiconductor device comprising a substrate, a plurality of dielectric films formed on the substrate, laid one upon another, and a fuse interconnect-wire formed above the substrate and covered...
7034378 Fuse structure used in an integrated circuit device  
A novel fuse structure. An optimal position of laser spot is defined above a substrate. A first conductive layer is formed on part of the substrate. A dielectric layer is formed on the substrate...
7026692 Low voltage non-volatile memory transistor  
A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate...
7026217 Method of forming an antifuse on a semiconductor substrate using wet oxidation of a nitrided substrate  
A method of producing an antifuse includes introducing nitrogen by ion implantation means into the substrate. An oxide dielectric layer is then formed on the nitrided substrate in a wet oxidation...
7005727 Low cost programmable CPU package/substrate  
A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends...
6991971 Method for fabricating a triple damascene fuse  
A method for fabricating a fuse for a semiconductor device. The method including: providing a substrate; forming a first dielectric layer on a top surface of said substrate; forming a dielectric...
6982219 Semiconductor device with fuse box and method for fabricating the same  
A semiconductor device comprises a semiconductor substrate having a bonding pad region; and a bonding pad and a fuse box formed in the bonding pad region. Thus, the chip size can be reduced and the...
6969659 FinFETs (Fin Field Effect Transistors)  
A FinFET structure that prevents parasitic electrical leakages between its gate region and its fin region and between its gate region and its epitaxial region (source/drain regions). The structure...
6964906 Programmable element with selectively conductive dopant and method for programming same  
A programmable element including a semiconductor material doped with a dopant that alters the resistance of the element when exposed to actinic radiation. Rather than producing a mechanical...
6949416 Method of manufacturing a semiconductor integrated circuit device  
Disclosed is a technique capable of enhancing the degree of freedom in the layout of a rerouting layer in a wafer level CSP in which defect repairing is performed by cutting a fuse. More...
6933591 Electrically-programmable integrated circuit fuses and sensing circuits  
Programmable fuses for integrated circuits are provided. The fuses may be based on polysilicon or crystalline silicon fuse links coated with silicide or other conductive thin films. Fuses may be...
6916711 EEPROM memory cell and method of forming the same  
An EEPROM memory cell and a method of forming the same are provided. A portion of a floating gate is formed on walls of a trench formed on the substrate. An inside of the trench is filled with a...
6913954 Programmable fuse device  
A fuse device including a transistor having a source, drain, and gate. The gate includes a first and second gate contact. A current may be run from the first gate contact to the second gate contact...
6911360 Fuse and method for forming  
An active fuse includes an active fuse geometry ( 120 ) that is used to form both a variable resistor ( 106 ) and a select transistor ( 110 ). In one embodiment, the active fuse geometry is formed...
6900102 Methods of forming double gate electrodes using tunnel and trench  
A double gate electrode for a field effect transistor is fabricated by forming in a substrate, a trench and a tunnel that extends from a sidewall of the trench parallel to the substrate. An...
Matches 1 - 50 out of 179 1 2 3 4 >