Patents in Class 438/278

Matches 1 - 50 out of 241

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Match	Document	Document Title
1	7588987	Semiconductor device and method for fabricating the same A semiconductor device and a method for fabricating the same selectively forms a nitride layer having high tensile stress in an NMOS transistor area, to thereby form a strained-silicon structure in...
2	7573095	Memory cells with improved program/erase windows A semiconductor structure includes a memory cell in a first region and a logic MOS device in a second region of a semiconductor substrate. The memory cell includes a first gate electrode over the...
3	7547941	NAND non-volatile two-bit memory and fabrication method A NAND non-volatile two-bit memory cell comprises a cell stack and two select stacks disposed on an active area of a substrate. Each select stack is respectively disposed on a side of the cell...
4	7504309	Pre-silicide spacer removal A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in...
5	7488653	Semiconductor device and method for implantation of doping agents in a channel A semiconductor device includes a substrate of a first type of conductivity provided with at least one gate on one of its faces, and at least two doped regions of a second type of conductivity for...
6	7442610	Low thermal budget fabrication method for a mask read only memory device A low thermal budget fabrication method for a mask ROM is described. The method includes providing a substrate having a gate oxide layer thereon. A first conductive layer is formed on the gate...
7	7396727	Transistor of semiconductor device and method for fabricating the same A transistor which may effectively control the short channel effect with a vertical transistor structure. This structure may prevent the degradation of a transistor's performance caused by the hot...
8	7393737	Semiconductor device and a method of manufacturing the same A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the...
9	7364973	Method of manufacturing NOR-type mask ROM device and semiconductor device including the same A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first...
10	7364951	Nonvolatile semiconductor memory device and method for manufacturing the same A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell...
11	7344951	Surface preparation method for selective and non-selective epitaxial growth According to one embodiment of the invention, a surface preparation method for selective and non-selective epitaxial growth includes providing a substrate having a gate region, a source region, and...
12	7320917	Semiconductor device and method for manufacturing the same Gate length is 110 nm±15 nm or shorter (130 nm or shorter in a design rule) or an aspect ratio of an area between adjacent gate electrode structures thereof (ratio of the height of the gate...
13	7300842	Method of fabricating a mask ROM A mask ROM and fabrication method thereof are disclosed, in which a bit line is formed of a conductive material such as polysilicon, by which a device size can be minimized, and by which resistance...
14	7259070	Semiconductor devices and methods for fabricating the same Disclosed are semiconductor devices and methods for fabricating the same. According to one embodiment, the method includes sequentially forming a gate insulation layer and a conductive layer on a...
15	7244653	Method and structure in the manufacture of mask read only memory A method and structure of manufacture of mask ROM device is provided. Firstly, a semiconductor structure is provided that comprises a first dielectric layer, a plurality of buried bit lines and a...
16	7230877	Method of making a semiconductor memory device A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor memory elements is disposed in the...
17	7179712	Multibit ROM cell and method therefor To increase the density of memory cells, a multibit memory cell ( 10, 50, 80, 110 ) can be manufactured by preventing the formation of at least one of the extension regions usually formed for the...
18	7169671	Method of recording information in nonvolatile semiconductor memory A nonvolatile semiconductor memory includes a transistor, one or two resistance-change portions, and one or two charge accumulation portions. The transistor has a control electrode, first main...
19	7163891	High density DRAM with reduced peripheral device area and method of manufacture A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the...
20	7132334	Methods of code programming a mask ROM device A method of code programming a mask read only memory (ROM) is disclosed. A method of the present invention includes forming a layer of developable anti-reflective coating over a plurality of code...
21	7122434	Method for generating an electrical contact with buried track conductors A semiconductor structure 300 comprises a plurality of first track conductors 303 , a plurality of second track conductors 304 , which are insulated with respect to the first track conductors ...
22	7094649	Method for forming multi-level mask ROM cell and NAND multi-level mask ROM The present invention relates to a multi-level read only memory cell that can store two bits and the fabrication method thereof. The multi-level ROM cell has the storage capacity of two bits and...
23	7084036	Data writing method for mask read only memory A data writing method for mask read only memory using different doses of ion implantations to perform the data writing of Mask Read Only Memory. A semiconductor substrate having a plurality of gate...
24	7064035	Mask ROM and fabrication thereof A Mask ROM and a method for fabricating the same are described. The Mask ROM comprises a substrate, a plurality of gates on the substrate, a gate oxide layer between the gates and the substrate, a...
25	7053447	Charge-trapping semiconductor memory device Memory cells are formed by preferably cylindrical recesses at the main surface of a semiconductor substrate, containing a memory layer sequence at sidewalls and a gate electrode and being provided...
26	7029956	Memory system capable of operating at high temperatures and method for fabricating the same A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a...
27	7008849	Method for providing bitline contacts in a memory cell array and a memory cell array having bitline contacts A method for providing bitline contacts in a memory cell array includes a plurality of bitlines disposed in a first direction, the bitlines being covered by an isolating layer, a plurality of...
28	7008848	Mask ROM fabrication method A mask read only memory (ROM) and a method of fabricating the same is provided. This mask ROM and related method is capable of reducing the pitch of buried impurity diffusion regions. In the mask...
29	6998316	Method for fabricating read only memory including a first and second exposures to a photoresist layer A fabrication method for a read only memory provides a substrate having a memory cell region and a periphery circuit region. A memory cell region has a memory cell array and the periphery circuit...
30	6991988	Static pass transistor logic with transistors with multiple vertical gates Static pass transistor logic having transistors with multiple vertical gates are described. Multiple vertical gates are edge defined with only a single transistor being required for multiple logic...
31	6989307	Mask ROM, and fabrication method thereof The present invention discloses a mask ROM which has excellent compatibility with a logic process and improves integration of a memory cell, and a fabrication method thereof. The mask ROM includes:...
32	6908819	Method of fabricating flat-cell mask read-only memory devices According to embodiments of the invention, a first gate insulating pattern and a mask pattern are sequentially stacked on a semiconductor substrate. Subsequently an impurity region is formed in the...
33	6902979	Method for manufacturing mask ROM A method for manufacturing a mask ROM of flat cell structure. The method includes the steps of: providing a semiconductor substrate having a flat cell array region and a peripheral circuit region;...
34	6893923	Reduced mask count process for manufacture of mosgated device A process for forming a power MOSFET enables the connection a metal gate electrode to the conductive polysilicon gates in the active area without an additional mask step. In the process, a groove...
35	6885066	SOI type MOSFET A buried insulating film is formed in an LDD region between a source region and a drain region, and a non-doped silicon film is formed in the SOI layer above the buried insulating film. The SOI...
36	6875659	Methods of code programming a mask ROM A method of code programming a mask read only memory (ROM) is disclosed. According to the method, a first photoresist layer is formed over word lines and a gate oxide layer of a substrate already...
37	6870233	Multi-bit ROM cell with bi-directional read and a method for making thereof A multi-bit Read Only Memory (ROM) cell has a semiconductor substrate of a first conductivity type with a first concentration. A first and second regions of a second conductivity type spaced apart...
38	6867103	Method of fabricating an ESD device on SOI A method to form transistors having improved ESD performance in the manufacture of an integrated circuit device is achieved. The method includes providing a SOI substrate with a doped silicon layer...
39	6864142	Method to produce a factory programmable IC using standard IC wafers and the structure A method for programming a semiconductor element in a semiconductor structure such as an IC involves reducing the backside thickness of the substrate and directing an energy beam through the...
40	6808985	Products derived from embedded flash/EEPROM products A method of fabricating ROM products through the use of embedded flash/EEPROM prototypes is disclosed. This is accomplished by first forming a Flash/EEPROM prototype, performing programming...
41	6806142	Method for coding semiconductor permanent store ROM A method for manufacturing a ROM device includes a semiconductor substrate having an array of field-effect transistors within a ROM region. A first dielectric layer covers the array and all...
42	6800527	One time programmable semiconductor nonvolatile memory device and method for production of same A semiconductor nonvolatile memory device improving reproducibility and reliability of insulation breakage of a silicon oxide film and capable of reducing the manufacturing cost and a method for...
43	6780716	Chip differentiation at the level of a reticle A method for differentiating integrated circuits implementing identical functions by storage of a binary code in a non-volatile storage element provided in each circuit, including providing, for...
44	6762100	Mask ROM cell and method of fabricating the same Mask ROM cell and method of fabricating the same, is disclosed, including a semiconductor substrate of a first conductivity type, a plurality of impurity diffusion regions of a second conductivity...
45	6756275	Method for minimizing product turn-around time for making semiconductor permanent store ROM cell A method for manufacturing a ROM device includes a semiconductor substrate having an array of field-effect transistors within a ROM region. A first dielectric layer covers the array of field-effect...
46	6753235	Method of manufacturing CMOS thin film transistor A method of manufacturing a CMOS TFT including forming first and second semiconductor layers on an insulating substrate using a first mask, respectively, the substrate having first and second...
47	6743679	Integrated circuit devices with high and low voltage components and processes for manufacturing these devices The present invention includes a technique for making a dual voltage integrated circuit device. A gate dielectric layer is formed on a semiconductor substrate and a gate material layer is formed on...
48	6727145	Method for fabricating post-process one-time programmable read only memory cell The present invention generally relates to a method for fabricating a post-process one-time programmable (OTP) read only memory cell (ROM cell). The OTP ROM cell has two oxide layers positioned on...
49	6723649	Method of fabricating a semiconductor memory device A method of fabricating a semiconductor memory device, particularly a mask ROM. A sacrificial oxide layer is formed on a silicon substrate and then a photoresist layer is formed on the sacrificial...
50	6713821	Structure of a mask ROM device A mask ROM device is described. The mask ROM device includes a substrate, a gate, a double diffused source/drain region that comprises a first doped region and a second doped region, a channel...

Matches 1 - 50 out of 241

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