|
Match
|
Document |
Document Title |
|
|
7622771 |
Semiconductor apparatus
A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer provided on a major surface of the first semiconductor layer, a third semiconductor layer provided on...
|
|
|
7615449 |
Semiconductor device having a recess channel transistor
The semiconductor device having a recess channel transistor includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower...
|
|
|
7612431 |
Trench polysilicon diode
Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second...
|
|
|
7611949 |
Method of fabricating metal-oxide-semiconductor transistor
A method of fabricating a metal-oxide-semiconductor (MOS) transistor is provided. First, a patterned hard mask layer with an opening therein is formed over the substrate. A spacer is formed on the...
|
|
|
7608510 |
Alignment of trench for MOS
Manufacturing a power transistor by forming a gate structure on a first layer, forming a trench in the first layer, self aligned with the gate structure, and forming part of the transistor in the...
|
|
|
7605036 |
Method of forming floating gate array of flash memory device
The method of forming a floating gate array of a flash memory device includes: (a) forming a plurality of device isolations, which define active device regions, in a semiconductor substrate, the...
|
|
|
7602014 |
Superjunction power MOSFET
An embodiment of an MOS device includes a semiconductor substrate of a first conductivity type, a first region of the first conductivity type having a length L acc and a net active dopant...
|
|
|
7601596 |
Semiconductor device with trench transistors and method for manufacturing such a device
According to one embodiment, a method for manufacturing a semiconductor device includes forming trenches in a first side of a semiconductor material and forming a thick oxide layer on the trenches...
|
|
|
7601595 |
Surround gate access transistors with grown ultra-thin bodies
A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to...
|
|
|
7595241 |
Method for fabricating silicon carbide vertical MOSFET devices
A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region...
|
|
|
7588985 |
Method for fabricating fin transistor
A method for fabricating a fin transistor includes patterning a first pad layer provided over a substrate using an isolation mask, etching the substrate using the isolation mask and the first pad...
|
|
|
7588977 |
Method of fabricating a MOS field effect transistor having plurality of channels
A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are...
|
|
|
7585711 |
Semiconductor-on-insulator (SOI) strained active area transistor
A selectively strained MOS device such as selectively strained PMOS device making up an NMOS and PMOS device pair without affecting a strain in the NMOS device the method including providing a...
|
|
|
7585705 |
Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop
A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD...
|
|
|
7582531 |
Method for producing a buried semiconductor layer
A method for producing a region of increased doping in an n-doped semiconductor layer which is buried in a semiconductor body of a vertical power transistor and which is arranged between a p-doped...
|
|
|
7582519 |
Method of forming a trench structure having one or more diodes embedded therein adjacent a PN junction
A semiconductor structure is formed as follows. A semiconductor region is formed to have a P-type region and a N-type region forming a PN junction therebetween. A first trench is formed extending...
|
|
|
7579650 |
Termination design for deep source electrode MOSFET
A power semiconductor device that includes a plurality of source trenches that extend to a depth below the gate electrodes and a termination region that includes a termination trench that is as...
|
|
|
7579648 |
Semiconductor device having a channel pattern and method of manufacturing the same
A semiconductor device may include a tubular channel pattern vertically extending from a semiconductor substrate. A gate insulation layer may be provided on faces exposed through the channel...
|
|
|
7566620 |
DRAM including a vertical surround gate transistor
DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect on the reduced size memory cells. In...
|
|
|
7566619 |
Methods of forming integrated circuit devices having field effect transistors of different types in different device regions
A method of forming an integrated circuit device includes forming a non-planar field-effect transistor in a cell array portion of a semiconductor substrate and forming a planar field-effect...
|
|
|
7564099 |
Monolithic MOSFET and Schottky diode device
A Schottky diode is integrated into a planar or trench topology MOSFET having parallel spaced source regions diffused into spaced base stripes. The diffusions forming the source and base stripes...
|
|
|
7557406 |
Segmented pillar layout for a high-voltage vertical transistor
In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of...
|
|
|
7557006 |
Methods of forming field effect transistors
A mass of material is formed over a semiconductor substrate. Semiconductive material is formed laterally proximate the mass of material. A space is provided laterally between the mass of material...
|
|
|
7553731 |
Method of manufacturing semiconductor device
A semiconductor device having SJ structure has a peripheral region having a higher withstand voltage than the withstand voltage of the cell region. A semiconductor upper layer including second...
|
|
|
7550791 |
Transistor and its method of manufacture
An embodiment includes a transistor and a method of manufacturing the transistor that includes carbon nano-tubes. The physical behavior of the carbon nano-tubes, particularly a bending action that...
|
|
|
7550352 |
MOS transistor having a recessed gate electrode and fabrication method thereof
A MOS transistor having a recessed gate electrode and a fabrication method thereof are provided. The MOS transistor includes an isolation layer formed at a predetermined region of a semiconductor...
|
|
|
7547585 |
P channel Rad Hard MOSFET with enhancement implant
A P channel vertical conduction Rad Hard MOSFET has a plurality of closely spaced base strips which have respective sources to form invertible surface channels with the opposite sides of each of...
|
|
|
7544572 |
Multi-operational mode transistor with multiple-channel device structure
A multiple operating mode transistor is provided in which multiple channels having different respective operational characteristics are employed. Multiple channels have threshold voltages that are...
|
|
|
7544570 |
Vertical-type metal insulator semiconductor field effect transistor device, and production method for manufacturing such transistor device
In a vertical-type metal insulator field effect transistor device having a first conductivity type drain region layer, a plurality of second conductivity type base regions are produced and arranged...
|
|
|
7544558 |
Method for integrating DMOS into sub-micron CMOS process
This invention is forming the DMOS channel after CMOS active layer before gate poly layer to make the modular DMOS process step easily adding into the sub-micron CMOS or BiCMOS process. And DMOS...
|
|
|
7544545 |
Trench polysilicon diode
Embodiments of the present invention include a method of manufacturing a trench polysilicon diode. The method includes forming a Nā(Pā) type epitaxial region on a N+(P+) type substrate and...
|
|
|
7541640 |
Vertical field-effect transistor and method of forming the same
A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a...
|
|
|
7541248 |
Integrated semiconductor device and method of manufacturing thereof
An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the...
|
|
|
7528040 |
Methods of fabricating silicon carbide devices having smooth channels
Methods of forming silicon carbide power devices are provided. An n ā silicon carbide layer is provided on a silicon carbide substrate. A p-type silicon carbide well region is provided on the n...
|
|
|
7528027 |
Structure and method for manufacturing device with ultra thin SOI at the tip of a V-shape channel
An SOI CMOS structure includes a v-shape trench in a pFet region. The v-shape trench has a surface in a (111) plane and extends into an SOI layer in the pFet region. A layer, such as a gate oxide...
|
|
|
7524726 |
Method for fabricating a semiconductor device
A process for fabricating a power semiconductor device is disclosed.
|
|
|
7524725 |
Vertical transistor of semiconductor device and method for forming the same
A vertical transistor of a semiconductor device and a method for forming the same are disclosed. The vertical transistor comprises a silicon fin disposed on a semiconductor substrate, a source...
|
|
|
7517758 |
Method of forming a vertical transistor
The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising...
|
|
|
7514327 |
Electronically scannable multiplexing device
An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable...
|
|
|
7514324 |
Selective epitaxy in vertical integrated circuit
Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are vertically oriented. These structures have...
|
|
|
7510954 |
Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward...
|
|
|
7510938 |
Semiconductor superjunction structure
Semiconductor structures and methods are provided for a semiconductor device ( 54 - 11, 54 - 12 ) employing a superjunction structure ( 81 ). The method comprises, forming ( 52 - 6 ) first...
|
|
|
7501323 |
Power MOSFET and method for forming same using a self-aligned body implant
A method for making a power MOSFET includes forming a trench in a semiconductor layer, forming a gate dielectric layer lining the trench, forming a gate conducting layer in a lower portion of the...
|
|
|
7498226 |
Method for fabricating semiconductor device with step gated asymmetric recess
A method for fabricating a semiconductor device with a step gated asymmetric recess is provided. The method includes: forming an organic bottom anti-reflective coating (BARC) layer over a...
|
|
|
7494875 |
Gate etch process for a high-voltage FET
A method, in one embodiment, includes etching first and second dielectric regions in a substantially isotropic manner through first and second openings of a mask layer to create first and second...
|
|
|
7491610 |
Fabrication method
A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure includes a semiconductor layer with a major...
|
|
|
7488651 |
Method of making vertical transistor structures having vertical-surrounding-gates with self-aligned features
The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with self-aligning features. The method provides...
|
|
|
7488650 |
Method of forming trench-gate electrode for FinFET device
A FinFET device having a trench-gate electrode, and a method of manufacture, is provided. The trench-gate electrode may be fabricated by forming a mask layer on a substrate having a semiconductor...
|
|
|
7482285 |
Dual epitaxial layer for high voltage vertical conduction power MOSFET devices
The epitaxial silicon junction receiving layer of a power semiconductor device is formed of upper and lower layers. The lower layer has a resistivity of more than that of the upper layer and a...
|
|
|
7482229 |
DRAM cells with vertical transistors
The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided...
|